US 7,397,715 B2 · Semiconductor memory device for testing redundancy cells

Abstract

Provided is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including regular cells; a redundancy memory cell array including redundancy cells for substituting for defective regular cells; a command decoder for generating an operation mode selection signal in response to command signals; a redundancy cell test controller for generating a test operation control signal and transmitting address signals in response to the operation mode selection signal; and a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal. All redundancy cells can be selected and tested based on the external command signal and the address signal, and thus it is possible to check all redundancy cells for defects in advance even after the semiconductor memory device is packaged, and to enable only non-defective redundancy cells to be substituted for defective regular cells. This increases the reliability of a repair operation.

Claims21

Dependent claims

A semiconductor memory device comprising:

a memory cell array including regular cells;
a redundancy memory cell array including redundancy cells for substituting for defective regular cells;
a command decoder for generating an operation mode selection signal in response to command signals;
a redundancy cell test controller for generating a test operation control signal in response to the operation mode selection signal and for transmitting address signals in response to the operation mode selection signal, wherein the redundancy cell test controller comprises:
a test operation controller for generating the test operation control signal when the same operation mode selection signal is consecutively received and terminating the generation of the test operation control signal when the same operation mode selection signal is received once more upon generating the test operation control signal;
and
an address signal transmitting unit for transmitting the address signals when the test operation control signal is received;
and
a redundancy decoder for decoding the address signals to select the redundancy cells in response to the test operation control signal.

6 more elements

A semiconductor memory device comprising:

a memory cell array including regular cells;
a redundancy memory cell array including first and second redundancy cells for substituting for defective regular cells;
a command decoder for generating an operation mode selection signal in response to command signals;
a redundancy cell test controller for transmitting address signals in response to the operation mode selection signal and a test mode selection signal, when a row or column test operation control signal is generated, wherein the redundancy cell test controller comprises:
a test operation controller for generating the row test operation control signal or the column test operation control signal in response to the operation mode selection signal and the test mode selection signal, wherein the test operation controller comprises:
an integrated test operation controller for generating the test operation control signal when the same operation mode selection signal is consecutively received, and terminating generating the test operation control signal when the same operation mode selection signal is received once more upon generating the test operation control signal;
and
a row and column test operation control signal generator for generating the row test operation control signal at a first state of the test mode selection signal and the column test operation control signal at a second state of the test mode
selection signal when the test operation control signal is generated, wherein the redundancy cell test controller further comprises:
a row address signal transmitting unit for transmitting the address signals in response to the row test operation control signal;
and
a column address signal transmitting unit for transmitting the address signals in response to the column test operation control signal;
a row redundancy decoder for decoding the address signals to select the first redundancy cells in response to the row test operation control signal;
and
a column redundancy decoder for decoding the address signals to select the second redundancy cells in response to the column test operation control signal.

12 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device for testing redundancy cells

Life of this patent

Semiconductor memory device for testing redundancy cells

Life of this patent

Abstract

Claims21