Back to results
US 7,397,712 B2Granted
Pre-emphasis for strobe signals in memory device
AssigneeMicron Technology, Inc.
InventorsJoo S Choi, Yogesh Sharma
Life of this patent
Estimating the term…
Abstract
Some embodiments of the invention include a memory device having a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals representing timing information of the data. The strobe terminals have a fixed signal level in an inactive mode of the memory device. The memory further includes a controller for reducing signal instability of the strobe signals when the memory device switches from the inactive mode to a data transfer mode. Other embodiments are described and claimed.
Claims44
A circuit comprising:
- a terminal;
- a first driver coupled between the terminal and a supply node for providing at the terminal a first strobe bit at a first time interval and a number of subsequent strobe bits after the first time interval;
- a second driver coupled in parallel with the first driver between the terminal and the supply node;
- and
- a pre-emphasis driver control unit coupled between the first and second drivers for controlling the second driver to influence a signal representing the first strobe bit.
2 more elements
A device comprising:
- a terminal;
- a first transistor coupled between the terminal and a supply node for providing at the terminal a number of strobe bits;
- a second transistor coupled between the terminal and the supply node;
- and
- a pre-emphasis driver control unit coupled between the first and second transistors for controlling the second transistor to influence a selected signal representing one of the strobe bits.
2 more elements
A memory device comprising:
- a memory array;
- a plurality of data terminals;
- a plurality of strobe terminals;
- a data transceiver circuit for transferring data between the data terminals and the memory array;
- and
- a strobe transceiver circuit for providing timing information of the data transferred at the data terminals, the strobe transceiver circuit including plurality of strobe output circuits, wherein each of the strobe output circuits includes:
- a first driver coupled between a supply node and a corresponding strobe terminal among the strobe terminals for providing a first strobe bit at a first time interval and a number of subsequent strobe bits after the first time interval;
- a second driver coupled in parallel with the first driver between the supply node and the corresponding strobe terminal;
- and
- a pre-emphasis driver control unit coupled between the first and second drivers for controlling the second driver to influence a signal representing the first strobe bit.
7 more elements
A memory device comprising:
- a plurality of memory cells;
- a plurality of data terminals;
- a plurality of strobe terminals;
- a data transceiver circuit for transferring data between the data terminals and the memory cells;
- and
- a strobe transceiver circuit for providing timing information of the data transferred at the data terminals, the strobe transceiver circuit including plurality of strobe output circuits, wherein at least one of the strobe output circuits includes:
- a first transistor coupled between a supply node and a corresponding strobe terminal among the strobe terminals for providing at the corresponding terminal a number of strobe bits;
- a second transistor coupled between the supply node and the corresponding strobe terminal;
- and
- a pre-emphasis driver control unit coupled between the first and second transistors for causing a first portion of a signal representing one of the strobe bits to be at a first signal level and for causing a second portion of the signal representing one of the strobe bits to be at a second signal level.
7 more elements
A system comprising:
- a process;
- and
- a memory device coupled to the processor, the memory device including,
- a plurality of memory cells;
- a plurality of data terminals;
- a plurality of strobe terminals;
- a data transceiver circuit for transferring data between the data terminals and the memory cells;
- and
- a strobe transceiver circuit for providing timing information of the data transferred at the data terminals, the strobe transceiver circuit including plurality of strobe output circuits, wherein at least one of the strobe output circuits includes:
- a first driver coupled between a supply node and a corresponding strobe terminal among the strobe terminals for providing at the corresponding terminal a number of strobe bits;
- a second driver coupled between the supply node and the corresponding strobe terminal;
- and
- a pre-emphasis driver control unit coupled between the first and second drivers for causing a first portion of a signal representing one of the strobe bits to be at a first signal level and for causing a second portion of the signal representing one of the strobe bits to be at a second signal level.
10 more elements
A method comprising:
- Propagating plurality of data bits to a plurality of data terminals;
- providing a plurality of strobe bits to a plurality of strobe terminals;
- the strobe bits corresponding to timing information of the data bits;
- causing a first portion of a selected signal to be at a first signal level, using a first driver coupled between a selected terminal of the plurality of strobe terminals and a supply node, wherein the selected signal corresponds to one selected strobe bit of the plurality of strobe bits;
- and
- causing a second portion of the selected signal to be at a second signal level, using a second driver coupled in parallel with the first driver between the selected terminal and the supply node, the second driver being controlled by a pre-emphasis driver control unit coupled between the first and second drivers.
3 more elements
Dependencies are inferred from the claim text.