Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same

An internal voltage level control circuit for controlling an activation and an inactivation of an internal voltage generating circuit which generates an internal voltage from an external power voltage,

• wherein the internal voltage is compared to at least one of a first predetermined voltage and a second predetermined voltage that define a predetermined voltage range,
• wherein when the internal voltage is within the predetermined voltage range, the internal voltage generating circuit is inactivated,
• wherein the internal voltage generating circuit includes a boost circuit for boosting the external power voltage, wherein the boost circuit is controlled based on at least one of the first predetermined voltage and the second predetermined voltage, and further comprising:
• a differential amplifier receiving an input of an internal signal having a voltage level based on the internal voltage and an input of a reference voltage signal having a voltage level that is at least one of the first predetermined voltage and the second predetermined voltage.

An internal voltage level control circuit, comprising:

• a comparator which compares an internal voltage to at least one of a first reference voltage and a second reference voltage that define a reference voltage range;
• an output control circuit which applies an external voltage to an output of the comparator when the comparator is inactivated;
• and
• an internal voltage generator that generates the internal voltage, wherein the internal voltage generator includes a boost circuit for boosting the external voltage, wherein the boost circuit is controlled based on at least one of the first reference voltage and the second reference voltage.

A semiconductor memory device, comprising:

• an internal voltage generating circuit that generates an internal voltage from an external voltage;
• and
• an internal voltage level control circuit for comparing the internal voltage to at least one of a first reference voltage and a second reference voltage that define a reference voltage range and for controlling an activation and an inactivation of the internal voltage generating circuit based on a comparison result, wherein when the internal voltage is within the reference voltage range, the internal voltage generating circuit is inactivated,
• wherein the internal voltage generating circuit includes a boost circuit for boosting the external voltage, wherein the boost circuit is controlled based on at least one of the first reference voltage and the second reference voltage, and
• wherein the internal voltage generating circuit includes a circuit for dropping the external voltage.

A semiconductor memory device, comprising:

• an internal voltage generating circuit that generates an internal voltage from an external voltage;
• and
• an internal voltage level control circuit for comparing the internal voltage to at least one of a first reference voltage and a second reference voltage that define a reference voltage range and for controlling an activation and an inactivation of the internal voltage generating circuit based on a comparison result, wherein when the internal voltage is within the reference voltage range, the internal voltage generating circuit is inactivated,
• wherein the internal voltage generating circuit includes a boost circuit for boosting the external voltage, wherein the boost circuit is controlled based on at least one of the first reference voltage and the second reference voltage;
• and
• a differential amplifier receiving an input of an internal signal having a voltage level based on the internal voltage and an input of a reference voltage signal having a voltage level that is at least one of the first reference voltage and the second reference voltage.

A semiconductor memory device, comprising:

• an internal voltage generating circuit that generates an internal voltage from an external voltage;
• and
• an internal voltage level control circuit for comparing the internal voltage to at least one of a first reference voltage and a second reference voltage that define a reference voltage range and for controlling an activation and an inactivation of the internal voltage generating circuit based on a comparison result, wherein when the internal voltage is within the reference voltage range, the internal voltage generating circuit is inactivated,
• wherein the internal voltage generating circuit includes a boost circuit for boosting the external voltage, wherein the boost circuit is controlled based on at least one of the first reference voltage and the second reference voltage, and
• wherein the semiconductor memory device is formed over a semiconductor substrate, and the semiconductor memory device includes a back bias generating circuit for generating, from the internal voltage, a back bias voltage which is lower than a ground level and supplied to the semiconductor substrate.

A semiconductor memory device, comprising:

• an internal voltage generating circuit that generates an internal voltage from an external voltage;
• and
• an internal voltage level control circuit for comparing the internal voltage to at least one of a first reference voltage and a second reference voltage that define a reference voltage range and for controlling an activation and an inactivation of the internal voltage generating circuit based on a comparison result, wherein when the internal voltage is within the reference voltage range, the internal voltage generating circuit is inactivated,
• wherein the internal voltage generating circuit includes a boost circuit for boosting the external voltage, wherein the boost circuit is controlled based on at least one of the first reference voltage and the second reference voltage, and
• wherein the internal voltage level control circuit includes:
• a comparator which compares the internal voltage to at least one of the first reference voltage and the second reference voltage;
• and
• an output control circuit which applies the external voltage to an output of the comparator when the comparator is inactivated.