Method for programming multi-level cell memory array
AssigneeMacronix International Co., Ltd.
InventorsChun Jen Huang, Chung Kuang Chen, Hsin Yi Ho
Life of this patent
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Abstract
A method for operating a charge-trapping multi-level cell (“MLC”) memory array comprises programming a first plurality of charge-trapping sites to a preliminary first-level value, programming a second plurality of charge-trapping sites to a preliminary second-level value, and programming a third plurality of charge-trapping sites to a final third-level value using a first programming scheme. Then, the first plurality of charge-trapping sites is programmed to a final first-level value and the second plurality of charge-trapping sites is programmed to a final second-level value using a second programming scheme.
Claims18
A method for operating a selected cell in an array of charge-trapping cells, wherein the selected cell includes first and second charge trapping sites programmable to different threshold voltages, including a lower level threshold and a higher level threshold, which represent programmed states, comprising:
- programming the first charge trapping site in the selected cell to a programmed state corresponding to the lower level threshold voltage range, said programming includes applying a first programming scheme adapted to setting a threshold voltage for the first charge trapping site at a level below the lower level threshold voltage range, and applying a second programming scheme adapted to setting the threshold voltage for the first charge trapping site within the lower level threshold voltage range;
- and
- programming the second charge trapping site in the selected cell to a programmed state corresponding to the higher level threshold voltage range, said programming includes applying a first programming scheme adapted to setting a threshold voltage for the second charge trapping site within the higher level threshold voltage range.
An integrated circuit comprising:
- a memory array including two-sided charge-trapping memory cells having respective first and second charge-trapping sites programmable to different threshold voltages, including a lower level threshold range and a higher level threshold range which represent programmed states;
- a biasing circuitry coupled to the memory array to apply biasing arrangements for programming the selected cell;
- and
- a control logic for operating the biasing circuitry for programming a selected cell in the memory array, the control logic including
- logic to program the first charge trapping site in the selected cell to a programmed state corresponding to the lower level threshold voltage range, by applying a first programming scheme adapted to setting a threshold voltage for the first charge trapping site at a value below the lower level threshold voltage range, and applying a second programming scheme adapted to setting the threshold voltage for the first charge trapping site at a value within the lower level threshold voltage range;
- and
- logic to program the second charge trapping site in the selected cell to a programmed state corresponding to the higher level threshold voltage range, by applying a first programming scheme adapted to setting a threshold voltage for the second charge trapping site at a value within the higher level threshold voltage range.
Dependencies are inferred from the claim text.