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US 7,397,701 B2Granted
Method and apparatus for operating a string of charge trapping memory cells
AssigneeMacronix International Co., Ltd.
InventorsChih Chieh Yeh, Wen Jer Tsai, Yi Ying Liao
Life of this patent
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Abstract
An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string. Each cell stores no more than a single charge storage state.
Claims36
A nonvolatile memory, comprising:
- a memory array including a plurality of columns, each column of the plurality of columns including a plurality of memory cells arranged in a series having a first end and a second end, each memory cell of the plurality of memory cells having at most a single charge storage state, each memory cell of the plurality of memory cells including:
- a substrate region including source and drain regions;
- a charge trapping structure storing the single charge storage state represented by a particular amount of charge at a particular part of the charge trapping structure;
- one or more storage dielectric structures at least partly between the charge trapping structure and the substrate region, and at least partly between the charge trapping structure and a source of gate voltage;
- a plurality of word lines coupled to said storage dielectric structures, the plurality of word lines acting as the source of gate voltage to the memory array;
- and
- logic coupled to the plurality of memory cells, said logic applying bias arrangements to the memory array to program, erase, and read the memory array.
4 more elements
A method of operating nonvolatile memory, comprising:
- applying bias arrangements to a memory array including a plurality of columns, each column of the plurality of columns including a plurality of charge trapping memory cells arranged in a series having a first end and a second end, each charge trapping memory cell of the plurality of charge trapping memory cells having at most a single charge storage state represented by a particular amount of charge at a particular part of a charge trapping structure of the charge trapping memory cell, including:
- applying a program bias arrangement to the memory array to program at most the single charge storage state for any memory cell of the memory array;
- and
- applying a read bias arrangement to the memory array to read at most the single charge storage state for any memory cell of the memory array.
1 more element
A method of manufacturing a nonvolatile memory, comprising:
- providing a memory array including a plurality of columns, each column of the plurality of columns including a plurality of memory cells arranged in a series having a first end and a second end, each memory cell of the plurality of memory cells having at most a single charge storage state, each memory cell of the plurality of memory cells including:
- a substrate region including source and drain regions;
- a charge trapping structure storing the single charge storage state represented by a particular amount of charge at a particular part of the charge trapping structure;
- one or more storage dielectric structures at least partly between the charge trapping structure and the substrate region, and at least partly between the charge trapping structure and a source of gate voltage;
- providing a plurality of word lines coupled to said storage dielectric structures, the plurality of word lines acting as the source of gate voltage to the memory array;
- and
- providing logic coupled to the plurality of memory cells, said logic applying bias arrangements to the memory array to program, erase, and read the memory array.
4 more elements
Dependencies are inferred from the claim text.