Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor
AssigneeSTMicroelectronics S.r.l.
InventorsLuigi Pascucci, Paolo Rolandi
Life of this patent
Estimating the term…
Abstract
A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells and with at least one associated row decoding circuit portion. Advantageously, the matrix includes at least one logic sector with pairs of rows or word lines being short-circuited with each other and referring to a respective biasing terminal, one for each pair, and in that the row decoding circuit portion includes a single select block which controls a single multiplexer for the logic sector for the regulation of the signals applied to the biasing terminals.
Claims25
A non-volatile electronic memory device comprising:
- at least one Electrically Erasable Programmable Read-Only Memory (EEPROM) NAND memory matrix being organized in rows and columns of memory cells and comprising at least one logic sector including at least one pair of rows of memory cells being short-circuited with each other, each pair of short-circuited rows of memory cells having a respective biasing terminal;
- and
- at least one row decoding circuit portion being associated with said at least one EEPROM NAND memory matrix and comprising a multiplexer, and a select block controlling said multiplexer for said at least one logic sector for regulation of a signal applied to the biasing terminal.
A non-volatile electronic memory device comprising:
- at least one Electrically Erasable Programmable Read-Only Memory (EEPROM) NAND memory matrix being organized in rows and columns of memory cells and comprising at least one logic sector including a plurality of pairs of rows of memory cells being short-circuited with each other, each pair of short-circuited rows of memory cells having a respective biasing terminal;
- and
- at least one row decoding circuit portion being associated with said at least one EEPROM NAND memory matrix and comprising a multiplexer including at least one pass transistor associated with each biasing terminal, and a select block controlling said multiplexer for said at least one logic sector for regulation of a signal applied to the biasing terminal.
A method of accessing an electronic memory device including at least one EEPROM NAND memory matrix being organized in rows and columns of memory cells and comprising at least one logic sector including at least one pair of rows of memory cells being short-circuited with each other, each pair of short-circuited rows of memory cells having a respective biasing terminal, and at least one row decoding circuit portion being associated with the at least one EEPROM HAND memory matrix and comprising a select block controlling a multiplexer for the at least one logic sector for regulation of a signal applied to the biasing terminal, the method comprising:
- using a protocol of an asynchronous type and a protocol of an extended type to address a number of memory addresses by at least loading an address register in two successive clock pulses.
Dependencies are inferred from the claim text.