Multi-bit-per-cell flash EEPROM memory with refresh

#1. Field of the Invention

#This invention relates to non-volatile semiconductor memory and more specifically to circuits and methods for detecting and correcting data errors in a memory storing multiple bits per memory cell.

#2. Description of Related Art

#FIG. 1 shows a block diagram of a multibit-per-cell memory in accordance with an embodiment of the invention.

#FIGS. 2A and 2B respectively show a row line voltage and a column line voltage during a write operation in the memory of FIG. 1.

#FIGS. 3A and 3B respectively show a row line voltage and a column line voltage during a read/refresh operation in the memory of FIG. 1.

#Use of the same reference symbols in different figures indicates similar or identical items.

#A multibit-per-cell memory in accordance with an embodiment of the invention partitions a range of threshold voltages of a memory cell into a set of allowed states that correspond to data values that can be stored in the memory cell and a set of forbidden zones. The allowed states are separated from each other by forbidden zones so that if the threshold voltage of a memory cell drifts it must cross through a forbidden zone before reaching another allowed state. A memory cell detected as having a threshold voltage in one of the forbidden zones indicates a data error that can be automatically corrected during a read or reported as an error for subsequent correction and refresh procedure.

#FIG. 1 illustrates a multibit-per-cell memory 100 in accordance with an embodiment of the invention. Memory 100 includes a memory array 140. In an exemplary embodiment of the invention, memory 100 is a flash EPROM, and array 140 includes hundreds or thousands of rows or columns of N-channel floating gate transistors (memory cells) organized into independently erasable sectors. Each row of memory cells has control gates coupled to a row line for the row, and each column of memory cells has drains coupled to a column line for the column. Each erasable sector has a source line coupled to the sources of memory cells in the sector. Row, column, and source drivers and decoders 130 are coupled to memory array 140 and generate voltages that are applied to selected row, column, and source lines in memory array 140 for erase, write, and read operations. For an erase, drivers and decoders 130 apply appropriate voltages to the memory cells in a sector to cause Fowler-Nordheim tunneling that removes electrons from the floating gates and reduces the threshold voltage of the memory cells in the sector. For a write operation, drivers and decoders 130 apply programming voltages to the row, column, and source lines coupled to a target memory cell to cause channel hot electron injection that increases the threshold voltage of the target memory cell to a level indicating a data value being written. As will be understood, applications of the invention. are not limited to flash EPROM of the exemplary embodiment but can be employed in a variety of memory architectures including but not limited to EPROM, E2PROM, and flash E2PROM.