Current sensing architecture for high bitline voltage, rail to rail output swing and Vcc noise cancellation
AssigneeSpansion LLC
InventorsSameer Wadhwa, Michael Achter, Bhimachar Venkatesh
Life of this patent
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AssigneeSpansion LLC
InventorsSameer Wadhwa, Michael Achter, Bhimachar Venkatesh
Estimating the term…
The present invention pertains to a circuit arrangement that, in one example, facilitates reading or determining an amount of current that flows through a memory cell when one or more voltages are applied to the cell. The amount of current resulting from the applied voltages is a function of the amount of charge stored within the cell, among other things, and the amount of stored charge represents information stored within the cell. As such, reading the resulting current allows data stored within the cell to be accessed and retrieved. It will be appreciated however, that use of the circuitry disclosed herein is not limited to memory applications. Rather, it can be used in any application where current sensing is required along with a regulated supply voltage.
A circuit for sensing a core current flowing through a bitline path and a memory cell in response to voltages applied to a gate of the cell and an acting drain of the cell, the magnitude of the core current also being a function of the amount of charge stored within the cell, the circuit comprising:
A circuit for sensing a core current flowing through a bitline path and a memory cell in response to voltages applied to a gate of the cell and an acting drain of the cell, the magnitude of the core current also being a function of the amount of charge stored within the cell, the circuit comprising:
A circuit for sensing a core current flowing through a bitline path and a multi-level memory cell in response to voltages applied to a gate of the cell and an acting drain of the cell, the magnitude of the core current also being a function of the amount of charge stored within the cell, the circuit comprising:
Dependencies are inferred from the claim text.