US 7,397,693 B2 · Semiconductor memory device with memory cells operated by boosted voltage

Abstract

A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

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Drawings

Claims17

Dependent claims

A semiconductor memory device comprising:

a plurality of static memory cells each comprising N-channel first and second driver MOS transistors, N-channel first and second transfer MOS transistors whose source-drain paths are coupled between drain electrodes of the driver MOS transistors and bit lines, and P-channel first and second load MOS transistors, and being placed in an array on a semiconductor substrate,
wherein source electrodes of the first and second driver MOS transistors are coupled to a first operating potential node, and source electrodes of the first and second load MOS transistors are coupled to a second operating potential node,
wherein a potential difference between the first operating potential node and the second operating potential node is larger than a high-level potential applied to gate electrodes of the first and second transfer MOS transistors or the bit lines,
wherein the first driver MOS transistor and the first transfer MOS transistor are formed in a first P-well region,
wherein the second driver MOS transistor and the second transfer MOS transistor are formed in a second P-well region,
wherein the first and second P-channel load MOS transistors are formed in a first N-well region, which is between the first and second P-well regions,
wherein a center line of diffusion layers of the first driver MOS transistor and the first transfer MOS transistor is parallel to a boundary between said first P-well region and said first N-well region,
wherein outer shapes of said diffusion layers are linearly symmetric against the center line,
wherein the gate width size of the N-channel driver MOS transistors is not more than 1.4 times the gate width size of the N-channel type transfer MOS transistors, and
wherein a first operating potential on the first operating potential node is generated from a third potential on a third operating potential node.

7 more elements

A semiconductor memory device comprising:

a plurality of static memory cells each comprising N-channel first and second driver MOS transistors, N-channel first and second transfer MOS transistors whose source-drain paths are coupled between drain electrodes of the driver MOS transistors and bit lines, and P-channel first and second load MOS transistors, and placed in an array on a semiconductor substrate,
wherein source electrodes of the first and second driver MOS transistors are coupled to a first operating potential node, and source electrodes of the first and second load MOS transistors are coupled to a second operating potential node,
wherein a potential difference applied between the first operating potential node and the second operating potential node is larger than a high-level potential applied to gate electrodes of the first and second transfer MOS transistors, and wherein the potential difference between the first operating potential node and the second operating potential node is larger during a write operation than during standby mode, and
wherein a first operating potential on the first operating potential node is generated from a third potential on a third operating potential node.

1 more element

Dependencies are inferred from the claim text.

Description9,166 words

Summary2,752 words

#1. Field of the Invention

#The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device preferable for a SRAM (Static Random Access Memory) which has secured the operational margin during write operation, and operates at a low voltage and a low electric power.

#2. Description of the Related Art

Brief description of the drawings25 figures

#FIG. 1 is a block diagram showing a memory cell array and peripheral circuits, and a configuration of power supply to be supplied thereto in Embodiment 1;

#FIG. 2 is a circuit configuration diagram of a SRAM memory cell to which the present invention is applied;

#FIGS. 3A to 3C are diagrams respectively showing the changes in electric potential of respective elements of the memory cell during operation of the memory in Embodiment 1;

Detailed description5,681 words

#FIG. 1 is a block diagram showing a memory cell array 30 constituting a SRAM memory in accordance with the present invention, a peripheral circuit 31 of the memory including a word driver, a decoder, and the like, a peripheral circuit 32 of the memory including a sense amplifier, a decoder, and the like, and the relationship between respective voltages Vdd and Vddm of power supply lines 2 and 4 to be supplied to the memory cell array 30 and the peripheral circuits 31 and 32. A voltage Vdd′ higher than the voltage Vdd of the power supply line 2 for the peripheral circuits 31 and 32 other than the memory cell array is applied to the power supply line 4 for the memory cell array 30. Incidentally, the same ground voltage Vss is applied to the source line of memory cell driver MOS transistors in the memory cell array 30, and the ground lines for other peripheral circuits, which are not shown.

#The configuration of the memory cell of the SRAM memory in this embodiment is the same as that of the memory cell of the prior-art SRAM memory shown in FIG. 2, wherein one memory cell is composed of 6 transistors. Therefore, also in this embodiment, a description will be given to the memory cell by reference to FIG. 2. The same goes for other embodiments.

#In the memory cell of FIG. 2, the voltage of a word line WL is referred to as Vw; the voltages of bit lines BL and /BL, Vb1 and Vb2, respectively; the voltage of the power supply line 4 for the memory cell, Vddm; the voltage of the ground line 5 for the memory cell, Vssm; and the voltages of the data holding nodes 6 and 7 of the memory cell, Vn1 and Vn2, respectively. Further, the power supply voltage and the ground voltage of the peripheral circuits are referred to as Vdd and Vss, respectively.

Facts

Application

11/657,026Filed 24 Jan 2007 · continuation

Priority

JP 2001-17645312 Jun 2001

Published

US 2007/0133260 A114 Jun 2007

Granted

8 Jul 2008

Term ended

7 Jun 2022

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification5 codes

G11C 11/417
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction: for memory cells of the field-effect type
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
Y10S 257/903
Active solid-state devices, e.g. transistors, solid-state diodes: fET configuration adapted for use as static memory cell
G11C
Static stores

Family

Application10/163,310Parent of this continuation · filed 7 Jun 2002

Application10/926,032Parent of this continuation · filed 26 Aug 2004

US 2007/0133260 A1Pre-grant publication · published 14 Jun 2007

US 7,190,609 B2Parent of this continuation

US 6,795,332 B2Parent of this continuation

US 2002/0186581 A1Published application

US 2005/0024917 A1Published application

US 7,397,693 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

12 Jun 2001Priority claimedJP 2001-176453
24 Jan 2007Application filedUS 11/657,026
14 Jun 2007PublishedUS 2007/0133260 A1
6 Nov 2007Assigned to Renesas Technology Corp.assignment of assignor's interest
8 Jul 2008GrantedUS 7,397,693 B2
9 Sep 2010Assigned to Renesas Electronics Corporationchange of name
9 Sep 2010Assigned to NEC Electronics Corporationmerger
29 Nov 2017Assigned to Renesas Electronics Corporationchange of address
7 Jun 2022Term endedEstimated

Semiconductor memory device with memory cells operated by boosted voltage

Life of this patent

Semiconductor memory device with memory cells operated by boosted voltage

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims17

Description9,166 words

Drawings

Classification5 codes

Life of this patent

Description9,166 words