Static random access memory cell with improved stability

An integrated circuit comprising a plurality of memory cells, at least one of the plurality of memory cells comprising:

• a wordline;
• a first digital inverter, the first digital inverter including a first input and a first output, at least the first input having a capacitance;
• a second digital inverter, the second digital inverter including a second input and a second output, at least the second input having a capacitance;
• a first feedback connection, the first feedback connection connecting the first output to the second input and comprising a first resistive element;
• and
• a second feedback connection, the second feedback connection connecting the second output to the first input and comprising a second resistive element;
• wherein the memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline, and the first and second resistive elements are configured such that the first and second feedback connections have respective resistance-capacitance induced delays longer than the applied read voltage pulse.