Memory system combining flash EEPROM and FeRAM

A memory system comprising:

• a ferroelectric memory including a plurality of memory cells each including a ferroelectric capacitor and a cell transistor;
• a flash EEPROM including a plurality of memory cells each including a floating gate and configured to electrically erase and write data;
• a control circuit configured to control the ferroelectric memory and the flash EEPROM;
• and
• an interface circuit configured to communicate with an external point,
• wherein the ferroelectric memory includes a flag memory area in a part of the ferroelectric memory,
• the flag memory area includes a first area that stores write-end flag data that indicates that actual recording of the data into the flash BEPROM is completed, and
• the flag memory area includes a second area that stores write-begin flag data that indicates that actual recording of the data into the flash EEPROM is started.

A memory system comprising:

• a ferroelectric memory including a plurality of memory cells each including a ferroelectric capacitor and a cell transistor;
• a flash EEPROM including a plurality of memory cells each including a floating gate and configured to electrically erase and write data;
• a hard disk configured to magnetically store data;
• a control circuit configured to control the ferroelectric memory, the flash EEPROM, and the hard disk;
• and
• an interface circuit configured to communicate with an external point,
• wherein the ferroelectric memory includes a mapping memory area in the ferroelectric memory.

A memory system comprising:

• a ferroelectric memory including a plurality of memory cells including a ferroelectric capacitor and a cell transistor;
• a flash EEPROM including a plurality of memory cells each including a floating gate and configured to electrically erase and write data;
• a hard disk configured to magnetically store data;
• a control circuit configured to control the ferroelectric memory, the flash EEPROM, and the hard disk;
• and
• an interface circuit configured to communicate externally,
• wherein the ferroelectric memory includes a flag memory area in a part of the ferroelectric memory,
• the flag memory area includes a first area that stores write-end flag data that indicates that actual recording of the data into the flash EEPROM is completed, and
• the flag memory area includes a second area that stores write-end flag data that indicates that actual recording of the data into the hard disk is completed.

A memory system comprising:

• a ferroelectric memory including a plurality of memory cells each including a ferroelectric capacitor and a cell transistor;
• a hard disk configured to magnetically store data;
• a control circuit configured to control the ferroelectric memory and the hard disk;
• and
• an interface circuit configured to communicate with an external point,
• wherein the ferroelectric memory includes a mapping memory area in a part of the ferroelectric memory, and
• the mapping memory area stores logical to physical converted map data indicating a relationship between a physical address on the hard disk and an actual logical address.

A memory system comprising:

• a ferroelectric memory including a plurality of memory cells each including a ferroelectric capacitor and a cell transistor;
• a hard disk configured to magnetically store data;
• a control circuit configured to control the ferroelectric memory and the hard disk;
• and
• an interface circuit configured to communicate with an external point,
• wherein the ferroelectric memory includes a flag memory area in a part of the ferroelectric memory,
• the flag memory area includes a first area that stores write-begin flag data that indicates that actual recording of the data into the hard disk is started, and
• the flag memory area includes a second area that stores write-end flag data that indicates that actual recording of the data into the hard disk is completed.