Semiconductor memory array with serial control/address bus
AssigneeInfineon Technologies AG
InventorsHermann Ruckerbauer, Ralf Schledz, Johannes Stecker, Dominique Savignac, Georg Braun
Life of this patent
Estimating the term…
Abstract
A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
Claims17
A memory array for operation in a data storage system, comprising:
- a plurality of memory chips for the storage of user data, said plurality of memory chips being subdivided into chip groups, each chip group being associated with one signal lane;
- a memory controller for the control of the memory chips;
- and
- at least one unidirectional, serial signal line bus for control signals and address signals connected with the memory controller, each signal line bus for control signals and address signals being associated with a respective signal lane, the bus signal lines corresponding to the respective signal lane directly connecting exactly one memory chip of the respective chip group with the memory controller and, in the case a chip group comprises more than one memory chip, serially connecting the memory chips of the respective chip group with each other by respective 1-point-to-1-point connections.
A data storage system with a memory array, said memory array comprising:
- a plurality of memory chips for the storage of user data, said plurality of memory chips being subdivided into chip groups, each chip group being associated with one signal lane:
- a memory controller for the control of the memory chips;
- and
- at least one unidirectional, serial signal line bus for control signals and address signals connected with the memory controller, each signal line bus for control signals and address signals being associated with a respective signal lane, the bus signal lines corresponding to the respective signal lane directly connecting exactly one memory chip of the respective chip group with the memory controller and, in case a chip group comprises more than one memory chip, serially connecting the memory chips of the respective chip group with each other by respective 1-point-to-1-point connections.
Dependencies are inferred from the claim text.