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US 7,397,642 B2Granted
ESD protection circuit
AssigneeSilicon Integrated Systems Corp.
InventorsMing-Dou Ker, Chien-Ming Lee
Life of this patent
Estimating the term…
Abstract
An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit, and a trigger current generator. The object of the stacked MOS circuit is to be the first releasing path of the ESD current; the object of the trigger current generator is to generate the trigger current to turn on the stacked MOS circuit, and then the stacked MOS circuit would be the first releasing path of the ESD current.
Claims16
An ESD protection circuit, comprising:
- a trigger current generation circuit generating a trigger current;
- and
- a stacked MOS circuit that receives said trigger current, and then conducts electrically as a first releasing path of ESD;
- wherein said trigger current generation circuit comprises:
- a first resistor, having a first end connecting to a first power supply;
- a first capacitor, having a first end connecting to a second end of said first resistor;
- a first NMOS, having a gate connecting to said second end of said first resistor, and a substrate connecting to a source;
- a second resistor, having a first end connecting to a drain of said first NMOS, a second end connecting to said source of said first NMOS and a second end of said first capacitor, and said second end connecting to a ground;
- a third capacitor, having a second end connecting to said first end of said second resistor;
- a second capacitor, having a second end connecting to a first end of said third capacitor, and a first end connecting to a second power supply;
- a fourth capacitor, having a first end connecting to said first end of said second capacitor and said second power supply;
- and
- a third resistor, having a second end connecting to a second end of said fourth capacitor, and a first end connecting to said first power supply.
10 more elements
An ESD protection circuit, comprising:
- a trigger current generation circuit generating a trigger current, comprising:
- a first resistor, having a first end connecting to a first power supply;
- a first capacitor, having a first end connecting to a second end of said first resistor;
- a first NMOS, having a gate connecting to said second end of said first resistor, and a substrate connecting to a source;
- a second resistor, having a first end connecting to a drain of said first NMOS, a second end connecting to said source of said first NMOS and a second end of said first capacitor, and said second end connecting to a ground;
- a third capacitor, having a second end connecting to said first end of said second resistor;
- a second capacitor, having a second end connecting to a first end of said third capacitor, and a first end connecting to a second power supply;
- a fourth capacitor, having a first end connecting to said first end of said second capacitor and said second power supply;
- and
- a third resistor, having a second end connecting to a second end of said fourth capacitor, and a first end connecting to said first power supply;
- and
- a stacked MOS circuit that receives said trigger current, and then conducts electrically as a first releasing path of ESD, comprising:
- a second NMOS, having a drain connecting to said second power supply and a gate connecting to said second end of said fourth capacitor;
- and
- a third NMOS, having a drain connecting to a source of said second NMOS, a substrate connecting to a source, said substrate connecting a substrate of said second NMOS to said ground, and a gate connecting to said first end of said second resistor.
12 more elements
An ESD protection circuit, comprising:
- a first resistor, having a first end connecting to a first power supply;
- a first capacitor, having a first end connecting to a second end of said first resistor;
- a first NMOS, having a gate connecting to said second end of said first resistor, and a substrate connecting to a source;
- a second resistor, having a first end connecting to a drain of said first NMOS, a second end connecting to said source of said first NMOS and a second end of said first capacitor, and said second end connecting to a ground;
- a third capacitor, having a second end connecting to said first end of said second resistor;
- a second capacitor, having a second end connecting to a first end of said third capacitor, and a first end connecting to a second power supply;
- a fourth capacitor, having a first end connecting to said first end of said second capacitor and said second power supply;
- a third resistor, having a second end connecting to a second end of said fourth capacitor, and a first end connecting to said first power supply;
- a second NMOS, having a drain connecting to said second power supply and a gate connecting to said second end of said fourth capacitor;
- a third NMOS, having a drain connecting to a source of said second NMOS, a substrate connecting to a source, said substrate connecting a substrate of said second NMOS to said ground, and a gate connecting to said first end of said second resistor;
- and
- a diode, as a second releasing path of ESD.
9 more elements
Dependencies are inferred from the claim text.