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US 7,397,478 B2Granted
Various apparatuses and methods for switching between buffers using a video frame buffer flip queue
AssigneeIntel Corporation
InventorHong Jiang
Life of this patent
Estimating the term…
Abstract
A method, apparatus, and system are described in which a signal is generated to inhibit the execution of flip commands that cause a flip between buffers of a frame buffer. One or more of the flip commands and their associated instruction pointers may be preloaded into a frame buffer flip queue prior to removing the signal inhibiting the execution of the flip commands.
Claims18
An apparatus, comprising:
- inhibit logic coupled to a frame buffer that includes one or more buffers;
- a frame buffer flip queue having a depth to store three or more entries and that is coupled to the inhibit logic as well as to the frame buffer, wherein the inhibit logic is configured to inhibit the one or more buffers from switching on a vertical synchronization pulse and also configured to inhibit the frame buffer flip queue from advancing instruction pointer entries on the vertical synchronization pulse;
- and
- a writeback queue coupled to the inhibit logic and the frame buffer flip queue to communicate to software a timing information and an identity information regarding a flip between the one or more buffers.
1 more element
A method, comprising:
- generating a signal to inhibit the execution of flip commands that cause a flip between buffers of a frame buffer;
- generating a notification of when the flip between the buffers is complete;
- and
- preloading one or more of the flip commands and their associated instruction pointers into a queue prior to removing the signal inhibiting the execution of the flip commands.
1 more element
A computing system, comprising:
- a processor;
- a bus connected to the processor;
- and
- a chipset coupled to the bus and a display monitor, and the chipset contains:
- inhibit logic coupled to a frame buffer that includes one or more buffers;
- a frame buffer flip queue having a depth to store three or more entries and tat is coupled to the inhibit logic as well as to the frame buffer, wherein the inhibit logic is configured to inhibit the one or more buffers from switching on a vertical synchronization pulse and also, configured to inhibit the frame buffer flip queue from advancing instruction pointer entries on the vertical synchronization pulse;
- a writeback queue coupled to the inhibit logic and the frame buffer flip queue to communicate to software a timing information and an identity information regarding a flip between the one or more buffers;
- and
- a rendering engine coupled to the frame buffer to store rendered video data in the frame buffer for a visual display of video images on the display monitor.
6 more elements
Dependencies are inferred from the claim text.