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AssigneeElectronics and Telecommunications Research Institute
InventorsYoung Deuk Jeon, Seung Chul Lee, Kwi Dong Kim, Jong Kee Kwon, Jong Dae Kim
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A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage and removing a sampling error of the input voltage; N-bit flash ADCs of first to K-th stages receiving analog signals, converting them into digital signals and outputting the digital signals; N-bit multiplying digital-to-analog converters (MDACs) of first to K-th stages converting differences between the digital signals output from the N-bit flash ADCs and output signals of preceding stages back into analog signals and outputting the analog signals; and a three-stage amplifier connected to an output of the N-bit MDAC of the first stage at a first clock and an output of the SHA at a second clock, wherein intergers N>= and K>=2. An amplifier can be shared between an SHA and an MDAC of a first stage, thereby reducing power consumption and chip size. In the multi-bit pipeline ADC, an amplifier can be shared between an SHA consuming much power and an MDAC of a first stage, so that power consumption and chip size can be reduced.
A multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure, comprising:
Dependencies are inferred from the claim text.
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Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages: using time-division…
All stages comprising simultaneous converters: and delivering the same number of bits
Coding
About 5 months of term left · ends 2 Apr 2027 (estimated)
This application claims priority to and the benefit of Korean Patent Application No. 2006-0089083, filed Sep. 14, 2006, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure, and more particularly, to technology capable of minimizing power consumption and reducing a chip size by enabling sharing of an amplifier used in a multi-bit pipeline ADC.
The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
FIG. 1 is a circuit diagram of a conventional multi-bit pipeline analog-to-digital converter (ADC);
FIG. 2 is a circuit diagram of a multi-bit pipeline ADC having a shared amplifier structure according to an exemplary embodiment of the present invention;
Hereinafter, exemplary embodiments of the present invention will be described in detail. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms. Therefore, the following embodiments are described in order for this disclosure to be complete and enabling to those of ordinary skill in the art.
FIG. 2 is a circuit diagram of a multi-bit pipeline analog-to-digital converter (ADC) having a shared amplifier structure according to an exemplary embodiment of the present invention.
As illustrated in FIG. 2, the multi-bit pipeline ADC according to the present invention comprises a sample-and-hold amplifier (SHA) 10 of an input terminal sampling and holding an input analog voltage, digital correction logic 40 for correcting errors in digital signals, and several stages. Each stage comprises an N-bit flash ADC 20 and an N-bit multiplying digital-to-analog converter (MDAC) 30. The N-bit flash ADC 20 receives an input analog signal of the preceding stage, converts it into a digital signal and outputs the digital signal. The N-bit MDAC 30 converts a difference between the digital signal output from the N-bit flash ADC 20 and an output signal of the preceding stage back into an analog signal and inputs it to the next stage. According to non-overlapping clocks Q1 and Q2, the SHA 10 and the MDAC 30 of a first stage MDAC1 share an amplifier AMP1, and MDAC2, MDAC3, . . . , MDAC(K-1) and MDAC(K) share amplifiers AMP2, . . . , AMP(k+1)/2.