Arithmetic decode without renormalization costs
AssigneeLSI Logic Corporation
InventorsHarminder S. Banwait, Eric C. Pearson, Scott F. James
Life of this patent
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.
Claims18
An apparatus comprising:
- a first circuit configured to generate context information in response to one or more bins on a binary signal;
- and
- a second circuit configured to generate said binary signal in response to (i) one or more input bits on a bitstream signal and (ii) simultaneously performing in a single cycle, (a) an arithmetic decode of said context information and (b) a renormalization of said context information, wherein said second circuit is further configured to (i) perform said renormalization once per bin and (ii) read a predetermined number of said input bits while performing said renormalization once per bin.
An apparatus comprising:
- means for generating context information in response to one or more bins on a binary signal;
- and
- means for generating said binary signal in response to (i) one or more input bits on a bitstream signal and (ii) simultaneously performing in a single cycle, (a) an arithmetic decode of said context information and (b) a renormalization of said context information, wherein said means for generating said binary signal is further configured to (i) perform said renormalization once per bin and (ii) read a predetermined number of said input bits while performing said renormalization once per bin.
A method for context adaptive binary arithmetic decoding comprising the steps of:
- (a) generating context information in response to one or more bins on a binary signal;
- and
- (b) generating said binary signal in response to (i) one or more input bits on a bitstream signal and (ii) simultaneously performing in a single cycle, (a) an arithmetic decode of said context information and (b) a renormalization of said context information, wherein step (b) includes the sub-steps of (i) performing said renormalization once per bin and (ii) reading a predetermined number of said input bits while performing said renormalization once per bin.
Dependencies are inferred from the claim text.