Modulation methods and systems

#1. Field of the Invention

#The present invention relates to modulation methods and systems for recording digital data on an information medium such as an optical disc, more particularly to modulation methods and systems for minimizing a cumulative digital sum value (DSV) for high-density optical storage systems.

#2. Description of the Prior Art

#FIG. 1 shows a functional block diagram for EFM+modulation.

#FIG. 2 is a functional block diagram showing an embodiment of a modulation system m.

#FIG. 3 expresses an example of a portion of the code conversation table shown in FIG. 2.

#FIG. 2 is a block diagram showing an embodiment of a modulation system 20 in a high-density recording system. For example, in an HD-DVD recording system, 8-bit data words will be transformed into 12-bit code words through a modulation system 20 as shown in FIG. 2, and the 12-bit code words is for recording on an optical disc. During the modulation procedure, the 8bit data word B(t) associated with a current state S(t) read from a state register 22 is converted to a pre-connection word X(t) through a conversion table 21, and in the meanwhile, a next state S(t+1) is also derived and stored in the state register 22. FIG. 3 expresses an example of a portion of the code conversation table 21. Concatenation rules for code words should be applied to connect the pre-connection code words X(t) derived from the conversion table 21. If adjoining pre-connection code words X(t) fit in some specific patterns, these pre-connection code words X(t) should be modified by a code connector 23. The code connector 23 generates and outputs pre-DSV code words Y(t), and if a pre-connection code word X(t) includes a DSV control bit, it also outputs a DSV control bit indicator IDDSV to a DSV controller 24. The DSV controller 24 determines the value of a current DSV control bit which minimizes the absolute cumulative DSV when it detects a subsequent DSV control bit from the code connector 23 or after a predetermined delay, and generate a post-DSV code word Z(t) according to the corresponding pre-DSV code word Y(t) and the determined current DSV control bit to achieve a minimized absolute cumulative DSV. The post-DSV code word Z(t) may be generated by modifying, inserting, or updating the corresponding pre-DSV code word Y(t) according to the determined current DSV control bit. Another way to generate the post-DSV code word Z(t) is to generate more than one possible code words corresponding to the corresponding pre-DSV code word Y(t). Z(t) is selected from one of the possible code words corresponding to the determined current DSV control bit. The conversion table 21, state register 22, and code connector 23 act as an encoder 25. In some embodiments, the timing for the DSV controller 24 to determine the value of the current DSV control bit may not depend upon the detection of the subsequent DSV control bit. The DSV controller 24 may wait until a second, a third, or a fourth subsequent DSV control bit has arrived, and then determine the current DSV control bit which minimizes the absolute cumulative DSV. It is also possible that the DSV controller 24 may determines more than one DSV control bit at a time. In some other embodiments such as a Blu-ray system, the current DSV control bit may be determined before the arrival of the subsequent DSV control bit.

#FIG. 4 shows an embodiment of the DSV controller 24, the DSV controller 24 includes a DSV control bit generator 151, a DSV control bit detector 152, a DSV location determiner 153, a storage device 154, and an insertion circuit 155. The DSV control bit generator 151 calculates a cumulative DSV for each possible value corresponding to a current control bit, and determines the current DSV control bit BDSV that minimizes the cumulative DSV. The DSV control bit detector 152 detects whether any DSV control bit exists in the current code word according to the DSV control bit indicator IDDSV. When a DSV control bit is detected, the DSV control bit detector 152 notifies the DSV location determiner 153. The storage device 154 stores each of the pre-DSV code words Y(t) generated by the code connector. In some embodiments, the storage device 154 comprises a series of pipe registers, delay registers, or shift registers, wherein each register stores one of the pre-DSV code word Y(t). In some other embodiments, the storage device 154 may be a first-in first-out (FIFO) memory, or a random access memory (RAM) with a write/read address generator. The number of registers is preferably greater than or equal to the maximum number of code words (or data words) between the occurrences of two consecutive DSV control bits. In an embodiment, the maximum number of code words between two consecutive DSV control bits may be the number of words in one frame, for example, 93 words, and it may be the number of words in two frames if considering that the DSV control bit in the frame sync field is used for ROPC (read optimum power calibration). The pre-DSV code words Y(t) are sequentially piped in the storage device 154. The DSV location determiner 153 records the location of each code word having a DSV control bit. For example, the DSV location determiner 153 keeps tracking the storage location of the code word having a first DSV control bit until receiving the code word having a second DSV control bit. When the DSV location determiner 153 receives a DSV control bit indicator IDDSV indicating the arrival of the second DSV control bit, it sends an enabling signal (E1, E2, . . . ,En) to a register of the storage device 154 storing the code word having the first DSV control bit. If the code word having the first DSV control bit is currently stored in the mth register of the storage device 154, the DSV location determiner 153 outputs the enabling signal Em to instruct the storage device 154 to allow the insertion of the determined current DSV control bit from the insertion circuit 155 to the mth register. By analogy, the second DSV control bit is determined and inserted into the corresponding register of the storage device 154 when the DSV location determiner 153 receives a DSV control bit indicator IDDSV indicating the arrival of the third DSV control bit, and so on. In this way, a DSV control bit is determined and inserted into the corresponding register of the storage device 154 when the DSV location determiner 153 receives a DSV control bit indicator IDDSV indicating the arrival of the subsequent DSV control bit. Instead of inserting a single DSV control bit into a code word, a code word might have two DSV control bits. In this case, it would be necessary to keep track of the individual bits within the code word to control the insertion of the two DSV control bits. In some other embodiments, the DSV control bits originally existed in the code words or data words are default values or arbitrary values, which will be modified in accordance to the determined DSV control bits generated by the DSV control bit generator. In some other embodiments, the digital words corresponding to the possible DSV control bits values are stored in the registers, then one of the digital words is selected in accordance to the determined DSV control bits generated by the DSV control bit generator. The digital words may be data words, final code words, or tentative code words, where the tentative code words are generated from the data words during modulation, and are used for generating the final code words.

#FIG. 5 is a block diagram showing an embodiment of the DSV control bit generator 151 in FIG. 4. Because a DSV control bit has two possible values, 0 and 1, the DSV control bit generator 151 determines the value which minimizes the absolute cumulative DSV. A partial DSV generator 1511 simultaneously generates two partial DSVs, PSD0 and PSD1, according to a tentative code word Y(t). If the tentative code word Y(t) does not have any DSV control bit, the two partial DSVs, PSD0 and PSD1, generated by the partial DSV generator 1511 are the same. If the tentative code word Y(t) has a DSV control bit as indicated by IDDSV, the two partial DSVs, PSD0 (assuming the current DSV control bit BDSV=0)and PSD1 (assuming the current DSV control bit BDSV=1), are generated by the partial DSV generator 1511, respectively. The DSV0 calculator 1512 adds the partial DSV PSD0 to the cumulative DSV DSVA0, or substrates the partial DSV PSD0 from the cumulative DSV DSVA0 according to the polarity of the cumulative DSV DSVA0. When the subsequent tentative code word Y(t) output from the code connector 23 does not have any DSV control bit, the cumulative DSV DSVA0 is selected from the value stored in the corresponding register 1516. After calculation, the value calculated by the DSVO calculator 1512 is stored in the register 1516 to update the original stored value. In the same manner, the DSV1 calculator 1513 adds the partial DSV PSD1 to the cumulative DSV DSVA1, or substrates the partial DSV PSD1 from the cumulative DSV DSVA1 according to the polarity of the cumulative DSV DSVA1. When the subsequent tentative code word Y(t) output from the code connector 23 does not have any DSV control bit, the cumulative DSV DSVA1 is selected from the value stored in the corresponding register 1517. The value calculated by the DSV1 calculator 1513 is then stored in the register 1517. When a subsequent DSV control bit is detected as indicated by IDDSV, the DSV comparator 1519 compares the cumulative DSVs DSV0 and DSV1 and chooses the minimum absolute value among which as the updated cumulative DSVA. Besides, the DSV comparator 1519 also designates the bit value corresponding to a minimum absolute value as the value of the current DSV control bit BDSV. Meanwhile, the two multiplexes, 1514 and 1515, select the updated cumulative DSVA as the cumulative DSVs of the two branches, that is, DSVA0 and DSVA1 for cumulative DSV calculations in the DSV0 calculator 1512 and DSV1 calculator 1513. After cumulative DSV calculation, the values calculated by the DSV0 calculator 1512 and DSV1 calculator 1513 are stored to the corresponding registers 1516 and 1517 as the newly updated cumulative DSVs. In this way, a DSV control bit could be determined by comparing the two branches of cumulative DSV calculations when a subsequent DSV control bit is detected.