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US 7,397,395 B2Granted
Representative majority voter for bus invert coding
AssigneeIntel Corporation
InventorsJames W Tschanz, Mircea R. Stan, Muhammad M Khellah, Yibin Ye, Vivek K De
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Abstract
In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.
Claims21
An apparatus comprising
- a representative majority voter gate to analyze bit transitions of a plurality of bits and generate an invert signal based thereon, wherein the plurality of bits are analyzed in groups, wherein said representative majority voter gate includes
- a plurality of transition gates to receive and analyze the bit transitions, wherein each gate receives and analyzes a group of bits and generates a result based on number of bits within the group that are transitioning;
- and
- at least one result gate to receive and analyze the results, wherein each of the at least one result gate receives and processes a group of results and generates a result based on number of results within the group that indicate a transition, and wherein a final result is the invert signal;
- and
- a conditional inverter to apply the invert signal to the plurality of bits.
3 more elements
An apparatus comprising
- a representative majority voter gate to analyze bit transitions of a plurality of bits and generate an invert signal based thereon, wherein the plurality of bits are analyzed in groups, wherein said representative majority voter gate analyzes transitions in groups, and wherein results are analyzed in groups in a tree structure until a single result is obtained, wherein the single result is the invert signal;
- and
- a conditional inverter to apply the invert signal to the plurality of bits.
An apparatus comprising
- a representative majority voter gate to analyze bit transitions of a plurality of bits and generate an invert signal based thereon, wherein the plurality of bits are analyzed in groups;
- a conditional inverter to apply the invert signal to the plurality of bits;
- a comparator to compare data bits to determine bits that have transitioned, wherein the comparison is between data bits previously sent and data bits preparing to be sent;
- and
- a bus to transmit the data bits from the conditional inverter and the invert signal.
2 more elements
A method comprising
- analyzing bit transitions of a plurality of bits, wherein the plurality of bits are analyzed in groups, wherein said analyzing includes analyzing the transitions in groups, and analyzing results in groups in a tree structure until a single result is obtained;
- generating an invert signal based on said analyzing, wherein said generating includes using the single result as the invert signal;
- and
- applying the invert bit and the plurality of bits to a conditional inverter.
1 more element
A method comprising
- analyzing bit transitions of a plurality of bits, wherein the plurality of bits are analyzed in groups;
- generating an invert signal based on said analyzing;
- applying the invert bit and the plurality of bits to a conditional inverter;
- comparing data bits previously sent and data bits preparing to be sent to determine bits that have transitioned;
- and
- transmitting data bits output from the conditional inverter and the invert signal.
3 more elements
A computer comprising:
- an off die memory device;
- and
- a processor die including a first function, a second function and an interconnect therebetween, wherein the first function includes
- a comparator to compare data bits to determine bits that have transitioned, wherein the comparison is between a first set of data bits previously sent and a second set of data bits preparing to be sent;
- a representative majority voter gate to analyze the transitions in order to determine if an invert bit should be set, wherein the representative majority voter gate analyzes the bits in groups;
- and
- a first conditional inverter to apply the invert bit to the second set of data bits to generate a third set of data bits;
- wherein the interconnect includes enough data lines to transmit the third set of data bits and an additional line to transmit the invert signal;
- and
- wherein the second function includes a second conditional inverter to receive the third set of data bits and the invert signal and apply the invert signal to the third set of data bits to generate a fourth set of data bits.
7 more elements
Dependencies are inferred from the claim text.