Auto-gain controlled digital phase-locked loop and method thereof

A method for controlling a digital PLL system, comprising:

• generating a phase difference signal according to an input signal and a clock signal;
• multiplying the phase difference signal by a first gain factor through a first multiplier of the digital PLL system;
• multiplying the phase difference signal by a second gain factor through a second multiplier of the digital PLL system;
• performing digital loop filtering upon outputs of the first multiplier and the second multiplier for providing an integral signal and a proportional signal and for generating a control signal according to the integral signal and the proportional signal;
• generating the clock signal according to the control signal through a digitally controlled oscillator of the digital PLL system;
• and
• updating the second gain factor according to the proportional signal.

A digital phase-locked loop (PLL) system, comprising:

• a phase detector, coupled to an input signal and a clock signal, for generating a phase difference signal indicating a phase difference between the input signal and the clock signal;
• a first multiplier, coupled to the phase detector, for multiplying the phase difference signal by a first gain factor;
• a second multiplier, coupled to the phase detector, for multiplying the phase difference signal by a second gain factor;
• a digital loop filter, coupled to the first multiplier and the second multiplier, for providing an integral signal and a proportional signal according to outputs of the first multiplier and the second multiplier and for generating a control signal according to the integral signal and the proportional signal;
• a digitally controlled oscillator, coupled to the digital loop filter, for generating the clock signal according to the control signal;
• an auto-gain control (AGC) unit, coupled to the first multiplier and the digital loop filter, for updating the first gain factor according to the integral signal.

A method for controlling a digital PLL system, comprising:

• generating a phase difference signal according to an input signal and a clock signal;
• multiplying the phase difference signal by a first gain factor through a first multiplier of the digital PLL system;
• multiplying the phase difference signal by a second gain factor through a second multiplier of the digital PLL system;
• performing digital loop filtering upon outputs of the first multiplier and the second multiplier for providing an integral signal and a proportional signal and for generating a control signal according to the integral signal and the proportional signal;
• generating the clock signal according to the control signal through a digitally controlled oscillator of the digital PLL system;
• and
• updating the first gain factor according to the integral signal.

A digital phase-locked loop (PLL) system, comprising:

• a phase detector, coupled to an input signal and a clock signal, for generating a phase difference signal indicating a phase difference between the input signal and the clock signal;
• a first multiplier, coupled to the phase detector, for multiplying the phase difference signal by a first gain factor;
• a second multiplier, coupled to the phase detector, for multiplying the phase difference signal by a second gain factor;
• a digital loop filter, coupled to the first multiplier and the second multiplier, for providing an integral signal and a proportional signal according to outputs of the first multiplier and the second multiplier and for generating a control signal according to the integral signal and the proportional signal;
• a digitally controlled oscillator, coupled to the digital loop filter, for generating the clock signal according to the control signal;
• an auto-gain control (AGC) unit, coupled to the second multiplier and the phase detector, for updating the second gain factor according to the phase difference signal.

A method for controlling a digital PLL system, comprising:

• generating a phase difference signal according to an input signal and a clock signal;
• multiplying the phase difference signal by a first gain factor through a first multiplier of the digital PLL system;
• multiplying the phase difference signal by a second gain factor through a second multiplier of the digital PLL system;
• performing digital loop filtering upon outputs of the first multiplier and the second multiplier for providing an integral signal and a proportional signal and for generating a control signal according to the integral signal and the proportional signal;
• generating the clock signal according to the control signal through a digitally controlled oscillator of the digital PLL system;
• and
• updating the second gain factor according to the phase difference signal.