Clock distribution circuit

#This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-271206 filed on Sep. 16, 2005, the entire contents of which are incorporated herein by reference.

#1. Field of the Invention

#The present invention relates to a circuit which generates and distributes high-speed and high-accuracy clock signals for analog circuits and digital circuits. In particular, the present invention relates to a technology for a high-speed interface circuit, a processor, and a clock distribution circuit that requires high-frequency clock signals.

#FIG. 1 is a diagram showing an example of a conventional configuration;

#FIG. 2A is a diagram showing a transistor-level embodiment of the amplitude amplification buffer and the transmission buffer. FIG. 2B is a diagram showing the clock generating circuit;

#FIG. 3 is a diagram showing the configurations of the amplitude amplification buffer and the transmission buffer of the present invention;

#Hereinafter, the preferred embodiments of the present invention are described in detail based on the diagrams.

#FIG. 2 shows an example configuration of a clock distribution circuit according to the present invention. FIG. 2A is a diagram showing an amplitude amplification buffer circuit 1 and a transmission buffer circuit 2. FIG. 2B is a diagram showing a clock generating circuit.

#The amplitude amplification buffer circuit 1 shown in FIG. 2A is composed of transistors. For example, it comprises a first MOSFET_Q1 (11 and 13), a second MOSFET Q2 (12 and 14), a third MOSFET_Q3 (15) and an inductor 4. Here, the first MOSFET is a P-channel MOSFET (P-channel metal-oxide semiconductor), hereinafter referred to as Q1. In addition, the second and third MOSFETs are N-channel MOSFETs (N-channel metal-oxide semiconductor), hereinafter referred to as Q2 and Q3 respectively.