Digital input buffer with glitch suppression
AssigneeNational Semiconductor Corporation
InventorVladislav Potanin
Life of this patent
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Abstract
A delay and deglitching circuit suppresses glitches occurring in a received digital signal while introducing a predetermined delay to the signal. The deglitching circuit comprises an RC filter and a Schmitt trigger. A node at the input of the Schmitt trigger fed by the RC filter is pulled to a high supply voltage or a low supply voltage when a glitch is removed or the input signal transitions. By setting the RC filter to initial conditions, multiple glitches can be removed with the same affectivity while reducing a sensitivity of the introduced delay to supply voltage variations.
Claims16
A circuit for deglitching and delaying a digital signal, comprising:
- a slow-charge circuit configured to receive the digital signal and provide a first signal at a first node in response to a transition in the digital signal, wherein the digital signal includes at least one glitch;
- a fast comparator circuit coupled to the slow-charge circuit at the first node, wherein the fast comparator circuit is configured to transition an output signal in response to the first signal reaching a predetermined threshold;
- a first switch coupled to the first node, wherein the first switch is configured to reset the first signal to an initial value after each glitch in the digital signal, wherein the first switch includes a first pair of serially coupled transistors configured to provide the high supply voltage to the first node, a first inverter coupled between an input node and a gate of one of the first pair of transistors, and a second inverter coupled between an output node and a gate of another of the first pair of transistors;
- and
- a second switch coupled to the first node, wherein the second switch is configured to set the first signal to a high supply voltage value when the output signal and the digital signal are both at a high level.
A method for deglitching and delaying a digital signal, comprising:
- increasing a voltage at a first node in response to a transition of the digital signal to a high level such that a glitch in the digital signal is insufficient to increase the voltage to a predetermined threshold;
- transitioning an output signal to the high level in response to the voltage at the first node reaching the predetermined threshold;
- resetting the voltage at the first node to an initial value after a glitch is encountered in the digital signal;
- and
- setting the voltage at the first node to a high supply voltage value when the output signal and the digital signal are both at the high level, wherein setting the voltage at the first node to the high supply voltage comprises closing a switch between the first node and a high supply voltage node in response to the digital signal and the output signal both having a high value, the switch including a first pair of serially coupled transistors configured to provide the high supply voltage to the first node, a first inverter coupled between an input node and a gate of one of the first pair of transistors, and a second inverter coupled between an output node and a gate of another of the first pair of transistors.
Dependencies are inferred from the claim text.