Clock jitter minimization in a continuous time sigma delta analog-to-digital converter

A wireless processing circuit, comprising:

• a wireless signal processor that processes a received wireless signal in preparation for analog to digital conversion;
• and
• an analog-to-digital converter communicatively connected to the wireless signal processor, the analog-to-digital converter comprising:
• a sigma delta modulator that produces a continuous time error signal based upon a conditioned analog signal produced by the wireless signal processor and a continuous time feedback signal;
• a loop filter that produces a conditioned output based upon the continuous time error signal;
• a analog-to-digital converter that produces a discrete time and quantized output based upon the conditioned output;
• and
• a digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter, the digital-to-analog converter comprising:
• a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal;
• a discrete time clock generator that generates, in response to receiving an assertion of the first data clock, an output pulse that is asserted for a fixed duration, the fixed duration being independent of a jitter of the first data clock, and
• a continuous time analog output, communicatively coupled to the discrete time digital signal input and the discrete time clock generator, producing the continuous time feedback signal during assertion of the output pulse, the continuous time feedback signal having a magnitude corresponding to the digital signal samples.