Method and relative circuit for generating a control voltage of a synchronous rectifier
AssigneeSTMicroelectronics S.r.l.
InventorsFabrizio Librizzi, Franco Lentini
Life of this patent
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Abstract
A control voltage for a synchronous rectifying transistor is generated with the desired anticipation time. The anticipation time is continuously controlled with a closed-loop technique by comparing it with the duration of a reference pulse. The resulting error signal is processed and provides the necessary correction to the MOSFET gate signal to equalize the actual anticipation time to the duration of the reference pulse.
Claims25
A method for generating a PWM control voltage for a synchronous rectifying transistor, the method comprising:
- generating a feedback logic signal having an active logic level when the PWM control voltage of the transistor and a voltage across conduction terminals of the transistor are at a null logic level;
- generating a first pulse logic signal having a first time duration corresponding to active edges of the PWM control voltage;
- and
- generating the PWM control voltage, a time duration of the active logic level of the PWM control voltage being determined based upon a difference between the time durations of the feedback and first pulse logic signals, for equalizing time durations of the feedback and first pulse logic signals.
A control circuit for a synchronous rectifying transistor comprising:
- a feedback signal generator for generating a feedback logic signal having an active logic level when a PWM control voltage of the transistor and a voltage across conduction terminals of the transistor are at a null logic level;
- a first pulse generator for generating a first pulse logic signal having a first duration corresponding to active edges of the PWM control voltage;
- and
- a voltage circuit receiving as input the feedback logic signal and the first pulse logic signal for generating the PWM control voltage, a duration of the active logic level of the PWM control voltage being determined based upon a difference between the time durations of the feedback and first pulse logic signals, for equalizing the time durations of the feedback and pulse logic signals.
A voltage converter comprising:
- a transistor;
- and
- a control circuit for said transistor comprising
- a feedback signal generator for generating a feedback logic signal having an active logic level when a PWM control voltage of the transistor and a voltage across conduction terminals of the transistor are at a null logic level,
- a first pulse generator for generating a first pulse logic signal having a first duration corresponding to active edges of the PWM control voltage, and
- a voltage circuit receiving as input the feedback logic signal and the first pulse logic signal for generating the PWM control voltage, a duration of the active logic level of the PWM control voltage being determined based upon a difference between the time durations of the feedback and first pulse logic signals, for equalizing the time durations of the feedback and pulse logic signals.
Dependencies are inferred from the claim text.