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US 7,397,286 B2Granted
Flip-flop circuit including latch circuits
AssigneeSanyo Electric Co., Ltd.
InventorHideaki Miyamoto
Life of this patent
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AssigneeSanyo Electric Co., Ltd.
InventorHideaki Miyamoto
Estimating the term…
A flip-flop circuit capable of inhibiting current consumption as well as the circuit scale from increase is provided. This flip-flop circuit comprises a first latch circuit including first and second inverter circuits. A first power supply line capable of switching a supplied potential between a fixing potential supplied for fixing the potentials of output nodes of the first and second inverter circuits and a floating potential supplied for floating the potentials of the output nodes of the first and second inverter circuits is connected to the first latch circuit.
A flip-flop circuit comprising a first latch circuit including a first inverter circuit and a second inverter circuit as well as a first equalizer circuit equalizing the potential of an output node of said first inverter circuit and the potential of an output node of said second inverter circuit with each other, wherein
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Digital stores in which the information is moved stepwise
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements
Details: modifications of generator to improve response time or to decrease power consumption
Bistable circuits: of the primary-secondary type
Term ended 3 Dec 2025 (estimated)
1. Field of the Invention
The present invention relates to a flip-flop circuit, and more particularly, it relates to a flip-flop circuit including latch circuits.
2. Description of the Background Art
FIG. 1 is a circuit diagram showing the structure of a shift register circuit employing flip-flop circuits according to a first embodiment of the present invention;
FIGS. 2 and 3 are voltage waveform diagrams for illustrating operations of the shift register circuit employing the flip-flop circuits according to the first embodiment of the present invention;
FIG. 4 is a block diagram showing the structure of a bidirectional shift register circuit employing flip-flop circuits according to comparative example of the first embodiment of the present invention;
Embodiments of the present invention are now described with reference to the drawings.
The circuit structure of a shift register circuit employing flip-flop circuits according to a first embodiment of the present invention is described with reference to FIG. 1.
As shown in FIG. 1, the shift register circuit is constituted of a plurality of stages of serially connected flip-flop circuits 1 according to the first embodiment. Each of the plurality of stages of flip-flop circuits 1 is constituted of two stages of delay latch circuits 2a and 2b. The delay latch circuits 2a and 2b are examples of the “first latch circuit” and the “second latch circuit” in the present invention respectively. The first-stage delay latch circuit 2a is formed to receive a prescribed input signal from a node D, latch the prescribed input signal for a constant period and thereafter output a signal obtained by inverting the potential of the prescribed input signal to the second-stage delay latch circuit 2b. The second-stage delay latch circuit 2b is formed to receive the output signal from the first-stage delay latch circuit 2a, latch the output signal for a constant period and thereafter output a signal obtained by inverting the potential of the output signal to the subsequent flip-flop circuit 1. The first-stage delay latch circuit 2a is constituted of a latch circuit 3, an n-channel transistor 4 and a transfer gate transistor 5. The n-channel transistor 4 is an example of the “first equalizer circuit” in the present invention.