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US 7,397,281 B2Granted
Input/output circuit of semiconductor memory device and input/output method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Hyun Choi, Young-Hun Seo
Life of this patent
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Abstract
An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.
Claims18
An input/output circuit for a semiconductor memory device, comprising:
- a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line;
- a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device;
- a capacitor coupled to the input/output signal line;
- and
- a load controller configured to couple the capacitor to a power supply in response to the input/output enable signal, the load controller including:
- a pad coupled to the input/output signal line;
- and
- a MOS transistor coupled between the pad and the power supply and responsive to the input/output enable signal;
- wherein the pad includes:
- a first layer coupled to the input/output signal line;
- and
- a second layer coupled to a drain of the MOS transistor.
9 more elements
An input/output method of a semiconductor memory device, the method comprising:
- buffering output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line;
- receiving input data from the input/output signal line and buffering the input data to transfer the buffered input data to the semiconductor memory device;
- and
- controlling a capacitance of the input/output signal line in response to the input/output enable signal;
- wherein controlling the capacitance of the input/output signal line further comprises increasing a capacitance between the input/output signal line and a low power supply and increasing a capacitance between the input/output signal line and a high power supply in response to the input/output enable signal.
2 more elements
An input/output circuit for a semiconductor memory device, comprising:
- a pad;
- a capacitor coupled to the pad;
- and
- a switching device configured to couple the capacitor to a power supply in response to an input/output enable signal when the input/output enable signal is in one of an input mode and an output mode;
- wherein the pad further comprises:
- a first layer coupled to an input/output signal line;
- and
- a second layer coupled to the switching device, the first layer and the second layer forming the capacitor.
5 more elements
An input/output circuit for a semiconductor memory device, comprising:
- a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line;
- a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device;
- and
- a load controller configured to control a load on the input/output signal line in response to the input/output enable signal, the load controller including:
- an inverter configured to invert the input/output enable signal;
- an NMOS capacitor having a first terminal coupled to the input/output signal line;
- a PMOS capacitor having a first terminal coupled to the input/output signal line;
- an NMOS transistor coupled between a second terminal of the NMOS capacitor and a low power supply, and responsive to the input/output enable signal;
- and
- a PMOS transistor coupled between a second terminal of the PMOS capacitor and a high power supply, and responsive to an output signal of the inverter.
7 more elements
An input/output circuit for a semiconductor memory device, comprising:
- a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line;
- a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device;
- and
- a load controller configured to control a load on the input/output signal line in response to the input/output enable signal, the load controller including:
- a pad coupled to the input/output signal line, the pad including:
- a first layer coupled to the input/output signal line;
- and
- a second layer coupled to a drain of the MOS transistor;
- and
- a MOS transistor coupled between the pad and a power supply, and responsive to the input/output enable signal.
7 more elements
An input/output method of a semiconductor memory device, the method comprising:
- buffering output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line;
- receiving input data from the input/output signal line and buffering the input data to transfer the buffered input data to the semiconductor memory device;
- and
- controlling a load of the input/output signal line in response to the input/output enable signal, including increasing the capacitance between the input/output signal line and a low power supply and increasing the capacitance between the input/output signal line and a high power supply in response to the input/output enable signal.
1 more element
An input/output circuit for a semiconductor memory device, comprising:
- a pad;
- a capacitor coupled to the pad;
- a switching device configured to couple the capacitor to a power supply in response to an input/output enable signal;
- a second capacitor coupled to the pad;
- and
- a second switching device configured to couple the second capacitor to a second power supply in response to the input/output enable signal.
3 more elements
Dependencies are inferred from the claim text.