Voltage level translator circuit with wide supply voltage range

A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the circuit comprising:

• an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith;
• a latch circuit coupled to the input stage and operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage;
• and
• a voltage clamp circuit connected between the input stage and the latch circuit, the voltage clamp circuit being operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies, the voltage clamp circuit comprising a sensing circuit operative to receive at least the first and second voltage supplies and to generate at least a first control signal indicative of the voltage difference between the first and second voltage supplies, the voltage across the input stage being controlled as a function of the first control signal;
• wherein the first control signal is indicative of at least one of:
• (i) whether or not the voltage difference between the first and second voltage supplies is less than or about equal to a specified amount;
• and (ii) whether or not the voltage difference between the first and second voltage supplies is greater than the specified amount.

A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the circuit comprising:

• an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith;
• a latch circuit coupled to the input stage and operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage;
• and
• a voltage clamp circuit connected between the input stage and the latch circuit, the voltage clamp circuit being operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies, the voltage clamp circuit comprising a sensing circuit operative to receive at least the first and second voltage supplies and to generate at least a first control signal indicative of the voltage difference between the first and second voltage supplies, the voltage across the input stage being controlled as a function of the first control signal;
• wherein the sensing circuit comprises:
• a first inverter comprising a PMOS device and an NMOS device, a source of the PMOS device being adapted for connection to the second voltage supply, a drain of the PMOS device being connected to a drain of the NMOS device at a first node, a gate of the PMOS device being adapted for connection to the first voltage supply, a source of the NMOS device being adapted for connection to a third voltage supply, and a gate of the NMOS device being adapted for connection to the first voltage supply;
• and
• at least a second inverter including an input connected to the first node and an output for generating the first control signal.

A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the circuit comprising:

• an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith;
• a latch circuit coupled to the input stage and operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage;
• and
• a voltage clamp circuit connected between the input stage and the latch circuit, the voltage clamp circuit being operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies;
• wherein the voltage clamp circuit comprises a sensing circuit operative to receive at least first and second signals, each of the first and second signals being indicative of an amplitude of the first and second voltage supplies, respectively, the sensing circuit being further operative to generate at least a first control signal indicative of the voltage difference between the first and second voltage supplies, the voltage across the input stage being controlled as a function of the first control signal.

A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the circuit comprising:

• an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith;
• a latch circuit coupled to the input stage and operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage;
• and
• a voltage clamp circuit connected between the input stage and the latch circuit, the voltage clamp circuit being operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies;
• wherein the voltage clamp circuit comprises:
• a sensing circuit operative to receive at least the first and second voltage supplies and to generate at least a first control signal representative of the voltage difference between the first and second voltage supplies;
• and
• switching circuitry operative to receive at least first and second reference signals and to generate an output reference signal, the switching circuitry being operative to select one of the at least first and second reference signals as the output reference signal in response to the at least first control signal, the voltage across the input stage being a function of the output reference signal of the switching circuitry.

A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the circuit comprising:

• an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith;
• a latch circuit coupled to the input stage and operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage;
• and
• a voltage clamp circuit connected between the input stage and the latch circuit, the voltage clamp circuit being operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies;
• wherein at least a portion of the voltage level translator circuit is configurable for being selectively turned off in response to at least a first control signal supplied to the voltage level translator circuit.

An integrated circuit comprising at least one voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply, the at least one voltage level translator circuit comprising:

• an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith;
• a latch circuit coupled to the input stage and operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage;
• and
• a voltage clamp circuit connected between the input stage and the latch circuit, the voltage clamp circuit being operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies;
• wherein the voltage clamp circuit in the at least one voltage level translator circuit comprises a reference selection circuit operative to receive at least first and second reference signals having first and second amplitudes, respectively, associated therewith, and to select one of the at least first and second reference signals as an output signal of the reference selection circuit based at least in part on the voltage difference between the first and second voltage supplies, the voltage across the input stage being a function of the output signal of the reference selection circuit.