US 7,397,271 B2 · Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal; a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state; and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state.

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Drawings

Claims12

Dependent claims

A semiconductor integrated circuit device comprising:

a combinational logic circuit including one or plural logic cells connected in series, wherein at least one of the logic cells includes
a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal,
a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state, and
a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state;
a first flip-flop circuit including a data input terminal to which an output signal of the combinational logic circuit is inputted and a clock input terminal to which a clock signal is inputted;
a second flip-flop circuit to which a clock control signal controlling whether the clock signal is supplied is inputted, the second flip-flop circuit outputting the clock control signal as an output signal in synchronization with a system clock signal;
an OR circuit to which the output signal of the second flip-flop circuit and the system clock signal are inputted, the OR circuit outputting the clock signal;
and
an inverter circuit to which the output signal of the second flip-flop circuit is inputted, the inverter circuit outputting a signal obtained by inverting the inputted signal as the circuit control signal.

6 more elements

A semiconductor integrated circuit device comprising:

a combinational logic circuit including one or plural logic cells connected in series, wherein at least one of the logic cells includes
a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal,
a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state, and
a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state;
a first flip-flop circuit including a data input terminal to which an output signal of the combinational logic circuit is inputted and a clock input terminal to which a clock signal is inputted;
a second flip-flop circuit to which a clock control signal controlling whether the clock signal is supplied is inputted, the second flip-flop circuit outputting the clock control signal as the circuit control signal in synchronization with a system clock signal;
a first low through latch circuit to which the output signal of the second flip-flop circuit is inputted as an input signal, the first low through latch circuit outputting the input signal when the system clock signal is low whereas the first low through latch circuit outputting a signal held in an immediately preceding state when the system clock signal is high;
and
an AND circuit to which the output signal of the first low through latch circuit and the system clock signal are inputted and which outputs the clock signal.

6 more elements

A semiconductor integrated circuit device comprising:

a combinational logic circuit including one or plural logic cells connected in series, wherein at least one of the logic cells includes
a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal,
a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state, and
a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state;
a latch circuit including a data input terminal to which an output signal of the combinational logic circuit is inputted as an input signal, the latch circuit outputting the input signal as an output signal when the standard cell is in an operation-enabled state whereas the latch circuit holding and outputting an immediately preceding state when the standard cell is in the operation-stopped state;
and
a first flip-flop circuit including a data input terminal to which the output of the latch circuit is inputted and a clock input terminal to which a clock signal is inputted.

4 more elements

A semiconductor integrated circuit device comprising:

a combinational logic circuit including one or plural logic cells connected in series, wherein at least one of the logic cells includes
a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal,
a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state, and
a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state;
and
a third flip-flop circuit to which an output signal from the combinational logic circuit is inputted, wherein
the third flip-flop circuit comprises
a master latch circuit including a data input terminal to which the output signal from the combinational logic circuit is inputted and a control terminal to which a logical AND signal obtained by performing a logical AND of the circuit control signal and a clock signal is inputted, and
a slave latch circuit including a data input terminal to which an output signal from the master latch circuit is inputted and a control terminal to which the clock signal is inputted.

6 more elements

Dependencies are inferred from the claim text.

Description16,450 words

Summary957 words

#This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Applications No. 2005-238747, filed on Aug. 19, 2005, and No. 2006-162560, filed on Jun. 12, 2006, the entire contents of which are incorporated by reference herein.

#1. Field of the Invention

#The present invention relates to a semiconductor integrated circuit device, and particularly relates to a semiconductor integrated circuit device including a combinational logic circuit.

Brief description of the drawings55 figures

#FIG. 1 shows an example of a circuit configuration of a semiconductor integrated circuit device according to a first embodiment;

#FIG. 2 shows an example of an operation timing chart of the semiconductor integrated circuit device shown in FIG. 1;

#FIG. 3 shows an example of a circuit configuration of a NAND circuit used in the semiconductor integrated circuit device shown in FIG. 1;

Detailed description14,360 words

#FIG. 1 shows an example of a circuit configuration of a combinational logic circuit in a semiconductor integrated circuit device according to this embodiment, and FIG. 2 shows an operation timing chart of the semiconductor integrated circuit device shown in FIG. 1.

#As shown in FIG. 1, a clock operating circuit in the semiconductor integrated circuit device according to this embodiment includes a flip-flop circuit FF10, a combinational logic circuit COM10, and a flip-flop circuit FF11.

#An input signal IN as a data signal is inputted to a data input terminal D of the flip-flop circuit FF10 and outputted as an output signal from a data output terminal Q in synchronization with a clock signal CLK1 inputted from a clock input terminal. The output signal outputted from the flip-flop circuit FF10 is inputted to the combinational logic circuit COM10.

Facts

Application

11/502,572Filed 11 Aug 2006

Priority

JP 2005-23874719 Aug 2005

Published

US 2007/0075738 A15 Apr 2007

Granted

8 Jul 2008

Term ended

6 Sep 2026

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 26 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification5 codes

H03K 19/17736
Arranged in matrix form: structural details of routing resources
H03K 19/1736
By wiring, e.g. uncommitted logic arrays: in which the wiring can be modified
H03K 19/17728
Structural details of logic blocks: reconfigurable logic blocks, e.g. lookup tables
H03K 19/1778
Arranged in matrix form: structural details for adapting physical parameters

Timeline

19 Aug 2005Priority claimedJP 2005-238747
11 Aug 2006Application filedUS 11/502,572
18 Oct 2006Assigned to Kabushiki Kaisha Toshibaassignment of assignor's interest
5 Apr 2007PublishedUS 2007/0075738 A1
8 Jul 2008GrantedUS 7,397,271 B2
6 Sep 2026Term endedEstimated, includes 26 days of adjustment

Semiconductor integrated circuit device

Life of this patent

Semiconductor integrated circuit device

Life of this patent

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims12

Description16,450 words

Drawings

Classification5 codes

Description16,450 words