Disconnection and short detecting circuit that can detect disconnection and short of a signal line transmitting a differential clock signal

A disconnection and short detecting circuit comprising:

• a first clock input end to which a non-inverting clock signal is inputted;
• a second clock input end to which inputted is an inverting clock signal, the phase of which is the reverse of that of said non-inverting clock;
• a first terminating resistor having one end connected to said first clock input end, and the other end to which a first potential is applied;
• a second terminating resistor having one end connected to said second clock input end, and the other end to which said first potential is applied;
• a first comparator having a first signal input end connected to said first clock input end, and a second signal input end connected to said second clock input end, and comparing potentials at said first and said second signal input ends and, based on the comparison result, outputting a first logical value or a second logical value different from said first logical value;
• a second comparator having a first signal input end connected to said first clock input end, and a second signal input end to which a second potential is applied, and comparing potentials at said first and said second signal input ends and, based on the comparison result, outputting said first or said second logical value;
• a third comparator having a first signal input end connected to said second clock input end, and a second signal input end to which a third potential is applied, and comparing potentials at said first and said second signal input ends and, based on the comparison result, outputting said first or said second logical value;
• a first signal output circuit for outputting a first signal if logical values outputted from said second and said third comparators are equal after a predetermined period of time or more;
• and
• a first flip-flop circuit having a clock input end for receiving an output of said first comparator, an input end to which applied is a voltage signal corresponding to said first or said second logical value, another input end for receiving said first signal, and an output end for outputting an output signal, said first flip-flop circuit outputting, as said output signal, a signal corresponding to said voltage signal if transition in a predetermined direction occurs in an output of said first comparator received at said clock input end, and negating said output signal if received said first signal.