Receiver circuit
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsTsuyoshi Ebuchi, Toru Iwata, Takefumi Yoshikawa
Life of this patent
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Abstract
In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
Claims9
A receiver circuit for receiving a receive signal that undergoes a given number or more transitions in a given time, comprising:
- a PLL circuit for generating a clock signal for processing the receive signal;
- a processing unit for processing said receive signal;
- and
- a signal detection unit that accepts said receive signal, and that includes a transition number detection circuit for detecting a number of transitions of a signal obtained based on said receive signal, and for classifying the number of transitions to plural set of regions which are related to a range of transition numbers and outputs a signal for controlling an operation of said processing unit based on the classified region,
- wherein said receive signal is a data signal and a clock signal received through a cable in which a plurality of transfer paths are integrated, and one of said data signal and said clock signal received through a cable is input to said signal detection unit.
Dependencies are inferred from the claim text.