MOS transistor characteristic detection apparatus and CMOS circuit characteristic automatic adjustment apparatus

A CMOS circuit characteristic automatic adjustment apparatus for automatically adjusting an operation state of the CMOS circuit so that a first MOS transistor in a target circuit in the CMOS circuit is operated in a saturated region, the apparatus comprising:

• a replica signal generation circuit for generating a replica signal capable of minimizing, if being received by the target circuit, a drain voltage of the first MOS transistor;
• a replica circuit for receiving the replica signal, the replica circuit being a replica of the target circuit and including a second MOS transistor corresponding to the first MOS transistor;
• a first voltage buffer for receiving a drain voltage of the first MOS transistor;
• a second voltage buffer for receiving a drain voltage of the second MOS transistor;
• a first MOS transistor group including at least one MOS transistor which has the same characteristics as those of the first MOS transistor and in which the same voltages as voltages applied to a gate and a source of the first MOS transistor are applied to a gate and a source, respectively, and an output voltage of the first voltage buffer is applied to a drain;
• a second MOS transistor group including at least one MOS transistor which has the same characteristics as those of the first MOS transistor and in which the same voltages as voltages applied to a gate and a source of the first MOS transistor are applied to a gate and a source, respectively, and an output voltage of the second voltage buffer is applied to a drain;
• a comparison circuit for comparing respective sizes of a first current flowing through the first MOS transistor group and a second current flowing through the second MOS transistor group;
• and
• an adjustment circuit for adjusting, based on a comparison result by the comparator circuit, an operation state of each of the target circuit and the replica circuit.