Monitoring system for detecting and characterizing classes of leakage in CMOS devices

#This invention generally relates to the manufacture of semiconductor devices, and more particularly, to a monitoring system for detecting and characterizing various classes of leakage in CMOS devices.

#As the scaling of integrated circuit continues to progress, CMOS devices become prone to many different types of leakage problems. Current technology having a gate dielectric thinner than 10 nm, a channel length shorter than 50 nm, a junction depth thinner than 20 nm, the threshold voltage of fast devices below 200 mV are typically subject to serious leakage related problems.

#Handling leakage problems has been profusely described in the art, as for instance, in U.S. Pat. No. 6,844,750 to Hsu et al. Therein is described a leakage monitoring apparatus that first measures die leakage and then generates digital keeper control bits to improve the performance of the dynamic circuits. More specifically, the sub-threshold leakage of CMOS devices on multiple locations of the die is simultaneously monitored. Based on the leakage information, keepers of dynamic circuits are properly sized to compensate for the leakage while maintaining the performance. The apparatus described uses a current mirror circuit to measure the sub-threshold leakage of pull down NMOS devices whose gates are connected to 150 mV. The patent is directed toward handling one specific class of circuit from being affected by sub-threshold leakage due to process variations. However, the apparatus described does not characterize other types of leakages, such as junction leakage, gate dielectric leakage. It neither addresses the problem of monitoring and quantifying the sub-threshold leakage of PMOS devices.

#The accompanying drawings, which are incorporated in and which constitute part of the specification, illustrate the presently preferred embodiments of the invention which, together with the general description given above and the detailed description of the preferred embodiments given below serve to explain the principles of the invention.

#FIGS. 1A-1B show respectively a schematic diagram and device cross-section of a conventional n-MOS capacitor monitor device.

#FIGS. 2A-2B show respectively a schematic diagram and a cross-sectional view of a prior art p-MOS capacitor leakage monitoring device.

#Hereinafter will be described the n-MOS and p-MOS leakage monitoring apparatus of the present invention. Since the circuit conFIGurations for testing n-MOS and p-MOS differ significantly from each other, they will be described independently.

#N-MOS Leakage Measuring Apparatus

#As previously stated, leakage monitoring devices of the class shown with reference to the circuits illustrated in FIGS. 1, 3 and 5, only one class of leakage, whether testing the gate, sub-threshold and junction leakage, respectively, can be tested at one time. The circuit is designed to test both normal and abnormal types of leakage for any classes of CMOS devices, which differ from each other by several orders of magnitude.