Semiconductor device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsManabu Ohnishi, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
Life of this patent
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Abstract
Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
Claims9
A semiconductor device formed by flip-chip bonding a semiconductor chip to a carrier used for external connection with the semiconductor chip, wherein:
- the semiconductor chip includes:
- a plurality of input/output (I/O) cells each including a circuit element and an electrode pad formed on the circuit element so that at least a portion of the electrode pad overlaps the circuit element in plan view, the plurality of I/O cells including first and second I/O groups each including at least two I/O cells, wherein
- the first I/O group includes at least two first I/O cells each having an inner electrode pad as the electrode pad and at least two second I/O cells each having an outer electrode pad as the electrode pad, and a plurality of electrode pads of the at least two first and second I/O cells included in the first I/O group are configured in a zigzag pad arrangement so as to form inner and outer pad arrays, and
- the second I/O group is formed in a region between a corner region of the semiconductor chip and the first I/O group, and includes at least two third I/O cells each having an outer electrode pad as the electrode pad, and said electrode pads included in the second I/O group are configured to form only outer pad array.
A semiconductor device formed by flip-chip bonding a semiconductor chip to a carrier used for external connection with the semiconductor chip, wherein:
- the semiconductor chip includes:
- a first plurality of I/O cells formed along a first side of the semiconductor chip and each including a circuit element and an electrode pad formed on the circuit element, the first plurality of I/O cells including first and second I/O groups each including at least two I/O cells, wherein
- the first I/O group includes at least two first I/O cells each having an inner electrode pad as the electrode pad and at least two second I/O cells each having an outer electrode pad as the electrode pad, and a plurality of electrode pads of the at least two first and second I/O cells included in the first I/O group are configured in a zigzag pad arrangement so as to form inner and outer pad arrays, and
- the second I/O group is formed in a region between a corner region of the semiconductor chip and the first I/O group, and includes at least two third I/O cells each having an outer electrode pad as the electrode pad, and said electrode pads included in the second I/O group are configured to form only outer pad array;
- and
- a second plurality of I/O cells formed along a second side of the semiconductor chip, the first and second sides of the semiconductor chip both sharing with the corner region of the semiconductor chip and each of the second plurality of I/O cells including a circuit element and an electrode pad formed on the circuit element, the second plurality of I/O cells including third and fourth I/O groups each including at least two I/O cells, wherein
- the third I/O group includes at least two fourth I/O cells each having an inner electrode pad as the electrode pad and at least two fifth I/O cells each having an outer electrode pad as the electrode pad, and a plurality of electrode pads of the at least two fourth and fifth I/O cells included in the third I/O group are configured in a zigzag pad arrangement so as to form inner and outer pad arrays, and
- the fourth I/O group is formed in a region between the corner region of the semiconductor chip and the third I/O group, and includes at least two sixth I/O cells each having an outer electrode pad as the electrode pad, and said electrode pads included in the fourth I/O group are configured to form only outer pad array.
Dependencies are inferred from the claim text.