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US 7,397,117 B2Granted
Chip package with die and substrate
AssigneeMegica Corporation
InventorsMou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
Life of this patent
Estimating the term…
Abstract
A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.
Claims19
A chip package comprising:
- a glass substrate;
- only one semiconductor die having a back surface joined with said glass substrate;
- a first polymer layer over said glass substrate and at a horizontal outside of said only one semiconductor die;
- a second polymer layer on a top surface of said only one semiconductor die, on said first polymer layer and over said horizontal outside, wherein said second polymer layer has a thickness between 5 and 100 micrometers;
- a first patterned metal layer over said second polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said first patterned metal layer is connected to said only one semiconductor die through an opening in said second polymer layer, and wherein said first patterned metal layer comprises sputtered copper and has a thickness between 1 and 150 micrometers;
- a third polymer layer on said first patterned metal layer, over said second polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said third polymer layer has a thickness between 1 and 150 micrometers;
- a second patterned metal layer on said third polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said second patterned metal layer is connected to said first patterned metal layer through an opening in said third polymer layer, and wherein said second patterned metal layer comprises an electroplated metal;
- an insulating layer on said second patterned metal layer, on said third polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein an opening in said insulating layer is over a pad of said second patterned metal layer and exposes said pad;
- and
- a solder bump over said pad of said second patterned metal layer and directly over said horizontal outside, wherein said solder bump is connected to said second patterned metal layer through said opening in said insulating layer.
7 more elements
A chip package comprising:
- a substrate;
- only one semiconductor die having a back surface joined with said substrate;
- a first polymer layer over said substrate and at a horizontal outside of said only one semiconductor die;
- a second polymer layer on a top surface of said only one semiconductor die, on said first polymer layer and over said horizontal outside, wherein said second polymer layer has a thickness of between 5 and 100 micrometers;
- a first patterned metal layer over said second polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said first patterned metal layer is connected to said only one semiconductor die through an opening in said second polymer layer, and wherein said first patterned metal layer comprises sputtered copper and has a thickness between 1 and 150 micrometers;
- a third polymer layer on said first patterned metal layer, over said second polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said third polymer layer has a thickness between 1 and 150 micrometers;
- a second patterned metal layer on said third polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein said second patterned metal layer is connected to said first patterned metal layer through an opening in said third polymer layer, and wherein said second patterned metal layer comprises an electroplated metal;
- an insulating layer on said second patterned metal layer, on said third polymer layer, over said top surface of said only one semiconductor die and over said horizontal outside, wherein an opening in said insulating layer is over a pad of said second patterned metal layer and exposes said pad;
- and
- a solder bump over said pad of said second patterned metal layer and directly over said horizontal outside, wherein said solder bump is connected to said second patterned metal layer through said opening in said insulating layer.
7 more elements
A chip package comprising:
- a substrate;
- a semiconductor die having a back surface joined with said substrate;
- a first polymer layer on a top surface of said semiconductor die and over a horizontal outside of said semiconductor die, wherein said first polymer layer has a thickness between 5 and 100 micrometers;
- and
- a first patterned metal layer on said first polymer layer, over said top surface of said semiconductor die and over said horizontal outside, wherein said first patterned metal layer is connected to said semiconductor die through an opening in said first polymer layer, wherein said first patterned metal layer comprises an electroplated metal and has a thickness between 1 and 150 micrometers, and wherein said first patterned metal layer comprises an inductor.
2 more elements
Dependencies are inferred from the claim text.