Folding chip planar stack package

#The present invention relates to a stack package. More particularly, the present invention relates to a folding chip planar stack package obtained by folding semiconductor chips.

#As generally known in the art, semiconductor packages have been developed to have a compact size while improving various electrical characteristics thereof. A representative example of the semiconductor package is a so-called BGA (ball grid array) package. As is known to those of ordinary skill in the art, a BGA package has a size similar to that of a semiconductor chip, so that the mounting space for the BGA package can be minimized. In addition, since the BGA package is electrically connected to external circuits through one or more solder balls on the BGA package, the transmission path between the BGA package solder ball and a semiconductor chip inside the package is kept as short as possible, so that the electrical characteristics of the BGA package can be improved.

#Recently, an FBGA (fine-pitch BGA) package has been suggested. The FBGA package not only has the advantages of the BGA package, but also realizes a fine pitch or close spacing of solder balls used for a signal/power input/output pins and is suitable for highly integrated semiconductor devices. FIG. 1 shows a representation of the structure of a typical FBGA package.

#The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

#FIG. 1 is a sectional view illustrating a convention BOC (board on chip) type FBGA (fine pitch ball grid array) package;

#FIG. 2 is a sectional view illustrating a conventional chip stack package;

#Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components, so repetition of the description on the same or similar components will be omitted.

#Referring now to FIG. 4 there is shown a sectional view of a folding chip planar stack package according to one embodiment of the present invention.

#As shown in FIG. 4, the folding chip planar stack package includes a substrate 45, first and second semiconductor chips 42 and 44 attached to an upper surface of the substrate 45 while being spaced in parallel to each other, a plurality of bonding wires 48 for electrically connecting the first and second semiconductor chips 42 and 44 with the electrical contacts on or in the substrate 45, a sealing material 49 for sealing the upper surface of the substrate 45 including the first and second semiconductor chips 42 and 44 and the bonding wire 48, and solder balls 50, which are attached to a lower surface of the substrate 45 so as to mount the folding chip planar stack package on an external circuit (not shown).