Semiconductor with damage detection circuitry

#During test and assembly operations, semiconductor devices are subject to large amounts of mechanical and thermal stresses. This is particularly true of devices with increasingly finer feature sizes, as the propensity for intra- and inter-level shorts caused by such operations drastically increases. Devices that have been diced, tested and assembled in packages often show signs of stress-related failures. These may be small microscopic cracks or highly visible stress-relief mechanisms such as film delamination, buckling, cracking, etc. In such cases, devices damage and attendant loss of useful life, leads to increased replacement costs. Moreover, these cracks and deformation-induced defects are difficult to detect, requiring large amounts of exhaustive failure analyses.

#The inventors have realized that there is a need for a method of quickly detecting assembly and test-related deformation of a semiconductor device that requires minimal engineering effort. According to one embodiment, the subject invention pertains to a chip edge and/or corner distortion and damage detection circuitry. This circuitry will assist in alleviating and resolving stress-induced failures from test and assembly operations. According to one embodiment, the damage detection circuits are placed along the periphery and corners of each device and requires no special or additional processing steps, thus its placement on the chip does not add to manufacturing costs. The detection circuits may be placed in close proximity to the seal ring at the device edge and corners. The detection circuitry allows electrical testing of the device in both wafer and package form, thus permitting the engineer to singulate the location of stress-induced defects and deformation such as cracking, delamination etc.

#FIG. 1 shows a top view of a semiconductor device comprising detection circuitry.

#FIG. 2 is a magnified view of an embodiment of corner damage detection circuitry.

#FIG. 3 shows a top view of a detection circuitry embodiment.

#According to one embodiment, the subject invention is directed to a semiconductor device comprising damage detection circuitry on at least a portion of a periphery of the semiconductor device. In a specific embodiment, the damage detection circuitry comprises one or more bands of conductive material disposed around the periphery of the semiconductor device. The detection circuitry is peripheral to the primary circuitry of the semiconductor device, and in those devices comprising a seal ring, inward from the seal ring.

#Turning to the figures, FIG. 1 shows a top view of a semiconductor device 100 comprising four conductive bands 101, 102, 103, and 104 around the periphery of the device 100. Those skilled in the art will appreciate that the bands may completely follow the periphery or a portion of the periphery. Each of the conductive bands 101, 102, 103 and 104 are separately conductively connected to pads 111, 112, 113, and 114, respectively. The conductive bands 101-104 are not conductively connected to each other unless damage to the semiconductor device has occurred. This feature allows the testing for damage by applying a voltage or current to two or more of the pads 111-114 to measure change in resistance and/or determine if any short or open has occurred between any of the conductive bands 101-104. A typical method of determining if any short has occurred is measuring any change in the initial resistance of the band (e.g. prior to assembly) comparative to post assembly and/or calculated values (pre and/or post assembly). Shorting of any of the bands is indicative of damage to the semiconductor device 100, thereby enabling the engineer to diagnose and correct the cause of such damage. The semiconductor device 100 is comprised of alternating metallization layers and dielectric layers (not shown). Furthermore, the semiconductor device 100 comprises a primary integrated circuit 120 formed among such alternating layers. The conductive bands 101-104 are not conductively connected to the primary integrated circuit 120 and are positioned peripheral to said primary integrated circuit 120. Surrounding the periphery of the semiconductor device 100 is a seal ring 125.

#The conductive bands 101-104 may be formed in multiple metallization layers and interconnected through vias in the dielectric layers. Therefore, testing of one band will enable the determination of damage present among any of the constituent layers. The configuration of the interconnected bands may take several forms, as will be readily appreciated by those skilled in the art in light of the teachings herein. In a specific embodiment, the configuration is a serpentine structure: that is, the individual band courses around the periphery at a first metallization layer and then connects to a band in a second metallization layer through one or more vias at a location along the band (typically at the end of the band), then courses around the second metallization layer and connects to a band on a third layer through one or more vias located at a location along the band, and so on, until a continuous serpentine like structure is constructed through the desired number of metallization layers. An example of a serpentine structure 500 is depicted in FIG. 5. It is noted that the structure is not drawn to scale nor are the bends of the band for each layer shown. However, the important feature depicted in FIG. 5 is how the interconnected bands can form a continuous structure that may be formed around each metallization layer and are interconnected to lower metallization layers throughout the desired dimension of the semiconductor device. Furthermore, as depicted in FIG. 5, the interconnection to other layers may be attained through one or more vias at any suitable location around the periphery.