Semiconductor devices with sidewall conductive patterns methods of fabricating the same

A non-volatile memory device comprising:

• a semiconductor substrate with an active region defined therein;
• a plurality of gate lines that cross over the active region, wherein each gate line comprises:
• a lower gate pattern on the active region of the substrate;
• a gate interlayer insulating layer on the lower gate pattern;
• an upper gate pattern on the gate interlayer insulating layer opposite the lower gate pattern and crossing over the active region of the substrate;
• and
• a sidewall gate pattern on at least a portion of sidewalls of the upper gate pattern and the lower gate pattern, and which electrically connects the upper gate pattern and the lower gate pattern;
• and
• a plurality of word lines that cross over the active region of the substrate and are between the gate lines, wherein each of the word lines comprises:
• a floating gate electrode on the active region of the substrate;
• a gate interlayer dielectric layer on the floating gate electrode;
• and
• a control gate electrode on the gate interlayer dielectric layer opposite to the floating gate electrode and crossing over the active region of the substrate,
• wherein an upper edge portion of the lower gate pattern is recessed relative to a lower edge portion of the lower gate pattern to define a ledge thereon, and the sidewall gate pattern is directly on the ledge and sidewall of the recessed upper edge portion of the lower gate pattern.