ESD protection structure using contact-via chains as ballast resistors

An ESD protection FET situated in a semiconductor die, said ESD protection FET comprising:

• a gate, a first active region, and a second active region, said gate comprising a plurality of gate fingers, one of said plurality of gate fingers being situated between said first active region and said second active region;
• a plurality of contact-via chains in series with said first active region, each of said plurality of contact-via chains comprising a contact, a first metal segment, and a via, said first metal segment being connected between said contact and said via, said first metal segment being situated in a first interconnect metal layer of said semiconductor die;
• a plurality of isolation regions surrounded by said first active region, each of said plurality of isolation regions being situated adjacent to at least one of said plurality of contact-via chains;
• wherein said first metal segment connects said contact only to said via, wherein said each of said plurality of contact-via chains forms a ballast resistor for increased ESD current distribution uniformity.