Non-volatile semiconductor memory
AssigneeNXP B.V.
InventorJose Solo De Zaldivar
Life of this patent
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Abstract
A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes, the first electrode of the coupling capacitor being electrically coupled with the polysilicon layer of the floating gate transistor, and the control electrode of the floating gate transistor forming the second electrode of the coupling capacitor. The invention also relates to a display device and an arrangement for controlling a display device, which each comprise a non-volatile semiconductor memory.
Claims20
A non-volatile semiconductor memory comprising:
- at least one EPROM/EEPROM memory cell that includes
- a floating gate transistor including a field effect transistor and a polysilicon layer;
- a first deposited metal interconnection layer having metal interconnects and a first metal electrode;
- a second deposited metal interconnection layer having a second metal electrode;
- a coupling capacitor that includes the first metal electrode, the second metal electrode, and a dielectric interposed between said first and second metal electrodes, the second metal electrode forming a control electrode of the floating gate transistor;
- a first via that electrically couples the first metal electrode to the polysilicon layer of the floating gate transistor;
- and
- a second via that electrically couples the second metal electrode to one of the metal interconnects of the first deposited metal interconnection layer.
A display device equipped with an arrangement for controlling the display device, which arrangement comprises:
- a non-volatile semiconductor memory including at least one EPROM/EEPROM memory cell containing
- a floating gate transistor having a field effect transistor and a polysilicon layer;
- a first deposited metal interconnection layer having metal interconnects and a first metal electrode;
- a second deposited metal interconnection layer having a second metal electrode;
- a coupling capacitor that includes the first metal electrode, the second metal electrode, and a dielectric interposed between said first and second metal electrodes, the second metal electrode forming a control electrode of the floating gate transistor;
- a first via that electrically couples the first metal electrode to the polysilicon layer of the floating gate transistor;
- and
- a second via that electrically couples the second metal electrode to one of the metal interconnects of the first deposited metal interconnection layer.
An arrangement for controlling a display device, which arrangement comprises:
- a non-volatile semiconductor memory including at least one EPROM/EEPROM memory cell containing
- a floating gate transistor having a field effect transistor and a polysilicon layer;
- a first deposited metal interconnection layer having metal interconnects and a first metal electrode:
- a second deposited metal interconnection layer having a second metal electrode;
- a coupling capacitor that includes the first metal electrode, the second metal electrode, and a dielectric interposed between said first and second metal electrodes, the second metal electrode forming a control electrode of the floating gate transistor;
- a first via that electrically couples the first metal electrode to the polysilicon layer of the floating gate transistor;
- and
- a second via that electrically couples the second metal electrode to one of the metal interconnects of the first deposited metal interconnection layer.
Dependencies are inferred from the claim text.