Barrier dielectric stack for seam protection

A semiconducting device comprising:

• a gate dielectric atop a semiconducting substrate, said semiconducting substrate containing source and drain regions adjacent said gate dielectric;
• a gate conductor atop said gate dielectric;
• a conformal dielectric passivation stack positioned on at least said gate conductor sidewalk, said conformal dielectric passivation stack comprising a first conformal dielectric layer having at least one first seam therein due to a step height of said gate conductor, and a second conformal dielectric layer having at least one second seam offset from said first seam, wherein said second conformal dielectric layer covers said at least one first seam to provide seams that are discontinuous through said conformal dielectric passivation stack thereby said conformal dielectric passivation stack contains a discontinuous electrical pathway;
• at least one other conformal dielectric layer that is seamless or having at least one other seam positioned between said first conformal dielectric layer and said second conformal dielectric layer, wherein said at least one other seam is offset from said at least one second seam;
• and
• a contact to said source and drain regions, wherein said conformal dielectric passivation stack substantially eliminates shorting between said contact and said gate conductor, wherein:
• said at least one other conformal dielectric layer, said first conformal dielectric layer, and said second conformal dielectric layer comprises a material selected from the group consisting of oxides, nitrides and oxynitrides;
• and
• said material of said at least one other conformal dielectric layer, said first conformal dielectric layer and said second conformal dielectric layer are a same composition.