Tunnel transistor having spin-dependent transfer characteristics and non-volatile memory using the same

A transistor comprising:

• a ferromagnetic semiconductor layer;
• a source that injects carriers into the ferromagnetic semiconductor layer;
• a drain that receives the carriers injected into the ferromagnetic semiconductor layer;
• and
• a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain, wherein:
• at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain;
• and
• transconductance can be controlled in accordance with the relative magnetization direction of the ferromagnetic semiconductor layer with respect to the ferromagnetic source or the ferromagnetic drain, or to the ferromagnetic source and the ferromagnetic drain, with the same bias being applied.

A transistor comprising:

• a ferromagnetic semiconductor layer;
• a source that injects carriers into the ferromagnetic semiconductor layer;
• a drain that receives the carriers injected into the ferromagnetic semiconductor layer;
• and
• a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain, wherein:
• at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain;
• and
• the magnetization configuration of the ferromagnetic semiconductor layer with respect to the ferromagnetic source or the ferromagnetic drain, or to the ferromagnetic source and the ferromagnetic drain, is parallel magnetization, a threshold voltage is set as a gate voltage for generating a predetermined current between the ferromagnetic source and the ferromagnetic drain by applying a current to the gate electrode.

A transistor comprising:

• a ferromagnetic semiconductor layer;
• a source that injects carriers into the ferromagnetic semiconductor layer;
• a drain that receives the carriers injected into the ferromagnetic semiconductor layer;
• and
• a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain, wherein:
• at least one of the source and the drain are a ferromagnetic source or a ferromagnetic drain;
• the transistor stores information in accordance with the relative magnetization direction of the ferromagnetic semiconductor layer with respect to the ferromagnetic source or the ferromagnetic drain, or to the ferromagnetic source and the ferromagnetic drain;
• and
• the transistor detects information stored in the transistor, based on the trans conductance of the transistor that depends on the relative magnetization direction of the ferromagnetic semiconductor layer with respect to the ferromagnetic source or the ferromagnetic drain, or to the ferromagnetic source and the ferromagnetic drain.

A memory circuit comprising:

• transistors, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• a ground line that collectively grounds the sources of a first group of transistors that are selected from the transistors;
• a word line that are collectively connected to the gates of the first group of transistors;
• and
• a bit line that are connected to the drains of the first group of transistors independently of one another, and are also collectively connected to a second group of transistors including transistors that do not belong to the first group.

A memory circuit comprising:

• transistors, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• a ground line that is collectively connected to the sources of transistor that belong to a transistor column comprising the transistors, the transistors belonging to the transistor column being aligned in one direction;
• a word line that is collectively connected to the gates of the transistors that belong to the transistor column;
• and
• bit lines that are connected to the drains of the transistors in the transistor column independently of one another.

A memory circuit comprising:

• transistors, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• a ground line that collectively grounds the sources of a first group of transistors that are selected from the transistors;
• a bit line that are collectively connected to the drains of the first group of transistors;
• and
• a word line that are connected to the gates of the first group of transistors independently of one another, and are also collectively connected to a second group of transistors including transistors that do not belong to the first group.

A memory circuit comprising:

• transistors being arranged in a matrix fashion, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• ground lines that are collectively connected to the sources of the transistors aligned in a column direction;
• word lines that are collectively connected to the gate electrodes of the transistors aligned in the column direction;
• and
• bit lines that are collectively connected to the drains of the transistors aligned in a row direction.

A memory circuit comprising:

• a first transistor and a second transistor being adjacent to each other, each of the first and the second transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• a word line that is respectively connected to the gate electrode of the first transistor and the gate electrode of the second transistor;
• a first bit line that is connected to the drain of the first transistor;
• a second bit line that is connected to the drain of the second transistor;
• a source that is shared between the first and second transistors;
• and
• a line that grounds the shared source, and extends in a direction perpendicular to the bit lines.

A memory circuit comprising:

• transistors, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• a ground line that is collectively connected to the sources of transistor that belong to a transistor row comprising the transistors, the transistors belonging to the transistor row being aligned in one direction;
• a bit line that is collectively connected to the drains of the transistors that belong to the transistor row;
• and
• word lines that are connected to the gates of the transistors in the transistor row independently of one another.

A memory circuit comprising:

• transistors being arranged in a matrix fashion, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• ground lines that are collectively connected to the sources of the transistors aligned in a row direction;
• word lines that are respectively connected to the gate electrodes of the transistors aligned in a column direction;
• and
• bit lines that are collectively connected to the drains of the transistors aligned in the row direction.

A memory circuit comprising:

• transistors being arranged in a matrix fashion, each of the transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• ground lines that are collectively connected to the sources of the transistors aligned in a row direction;
• word lines that are collectively connected to the gate electrodes of the transistors aligned in a column direction;
• and
• bit lines that are collectively connected to the drains of the transistors aligned in the row direction,
• ground lines adjacent to each other in the column direction being formed by one line among the ground lines.

A memory circuit comprising:

• a first transistor and a second transistor being adjacent to each other, each of the first and the second transistors including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• a word line that is collectively connected to the gate electrode of the first transistor and the gate electrode of the second transistor;
• a first bit line that is connected to the drain of the first transistor;
• a second bit line that is connected to the drain of the second transistor;
• a source that is shared between the first and second transistors;
• and
• a line that grounds the shared source, and extends in a direction parallel to the bit lines.

A memory element comprising:

• a transistor including a ferromagnetic semiconductor layer, a source that injects carriers into the ferromagnetic semiconductor layer, a drain that receives the carriers injected into the ferromagnetic semiconductor layer, and a gate electrode that applies a voltage for controlling conduction of the carriers flowing in the ferromagnetic semiconductor layer from the source to the drain;
• a first line that is connected to the gate electrode;
• a second line that is connected to the drain;
• and
• a third line that grounds the source.