Method for fabricating semiconductor device having capacitor
AssigneeHynix Semiconductor Inc.
InventorsSang-Do Lee, Sun-Woong Na, Dong-Ryeol Lee, Dong-Goo Choi
Life of this patent
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Abstract
A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer; forming a second etch stop layer over a top electrode of the capacitor; forming a fourth insulation layer over the third insulation layer and the second etch stop layer; and performing a plurality of etch steps to expose an upper surface of the bit line and an upper surface of the capacitor.
Claims18
A method for fabricating a semiconductor device, comprising:
- providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level;
- forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer;
- forming a second etch stop layer over a top electrode of the capacitor;
- forming a fourth insulation layer over the third insulation layer and the second etch stop layer;
- and
- performing a plurality of etch steps to expose an upper surface of the bit line and an upper surface of the capacitor.
A method for fabricating a semiconductor device, comprising:
- providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level, wherein first, second, and third insulation layers are formed over the bit line, the second insulation layer being a first etch stop layer;
- forming a second etch stop layer over a top electrode of the capacitor;
- forming a fourth insulation layer over the third insulation layer and the second etch stop layer;
- etching the fourth insulation layer to expose a portion of the second etch stop layer and a portion of the third insulation layer;
- etching the third insulation layer until the first etch stop layer is exposed;
- etching the first etch stop layer and the first insulation layer until an upper surface of the bit line is exposed using an etch gas having high selectivity to the second etch stop layer;
- and
- etching the second etch stop layer until the top electrode is exposed using an etch gas having high selectivity to the top electrode.
Dependencies are inferred from the claim text.