Manufacturing method for forming all regions of the gate electrode silicided
AssigneeRenesas Technology Corp.
InventorShigeki Komori
Life of this patent
Estimating the term…
Loading patent…
AssigneeRenesas Technology Corp.
InventorShigeki Komori
Estimating the term…
The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source/drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source/drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source/drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.
A manufacturing method of a semiconductor device, comprising the steps of:
A manufacturing method of a semiconductor device, comprising the steps of:
Dependencies are inferred from the claim text.