Methods of fabricating surrounded-channel transistors with directionally etched gate or insulator formation regions

A method of fabricating a transistor, the method comprising:

• forming an elongate stacked semiconductor structure on a substrate, the stacked semiconductor structure comprising a second semiconductor material region disposed on a first semiconductor material region;
• selectively doping the first semiconductor material region to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween;
• etching to expose a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions, wherein the etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions;
• forming an insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions;
• forming an insulation region in the hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions;
• forming a gate electrode that conforms to the insulation layer on top and sidewall surfaces of the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions;
• and
• forming source/drain regions in the second semiconductor material regions on respective sides of the gate electrode.