Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals
AssigneesInternational Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.
InventorsVictor Chan, Haining S. Yang, Yong M. Lee, Eng H. Lim
Life of this patent
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Abstract
Methods of fabricating a semiconductor device including a dual-hybrid liner in which an underlying silicide layer is protected from photoresist stripping chemicals by using a hard mask as a pattern during etching, rather than using a photoresist. The hard mask prevents exposure of a silicide layer to photoresist stripping chemicals and provides very good lateral dimension control such that the two nitride liners are well aligned.
Claims18
A method of fabricating a semiconductor device including a dual-hybrid liner over a PFET and an NFET, the method comprising:
- depositing a tensile silicon nitride layer over the PFET and the NFET;
- depositing a hard mask over the tensile silicon nitride layer, the hard mask including one of tetraethyl orthosilicate (TEOS), plasma-enhanced chemical vapor deposited (PECVD) silicon dioxide, carbon doped silicon dioxide and silicon carbide (SiC);
- removing the hard mask over the PFET to the tensile silicon nitride layer using a first photoresist mask;
- removing the first photoresist mask;
- etching to remove the tensile silicon nitride layer over the PFET to a silicide layer adjacent the PFET using the hard mask as a pattern;
- performing an annealing operation to remove damage to the silicide layer and reduce silicide resistance after etching to remove the tensile silicon nitride layer:
- depositing a compressive silicon nitride layer over the PFET and the NFET;
- removing the compressive silicon nitride layer over the NFET using a second photoresist mask;
- removing the second photoresist mask;
- and
- depositing an interlayer dielectric over the PFET and the NFET.
A method of inducing stress in a transistor channel of a PFET and an NFET, the method comprising:
- depositing a first silicon nitride layer over the PFET and the NFET;
- depositing a hard mask over the first silicon nitride layer;
- removing the hard mask over the PFET to the first silicon nitride layer;
- etching the first silicon nitride layer over the PFET to a silicide layer adjacent the PFET using the hard mask over the NFET as a pattern;
- performing an annealing operation to remove damage to the silicide layer and reduce silicide resistance after etching the first silicon nitride layer;
- and
- forming a second silicon nitride layer over the PFET.
A method of preventing exposure of a silicide layer adjacent a transistor during formation of a dual-hybrid liner to photoresist stripping chemicals, the method comprising:
- depositing a first silicon nitride layer over a first FET and a second FET;
- forming a hard mask over the first silicon nitride layer over the first FET;
- using the hard mask as a pattern, etching the first silicon nitride layer over the second FET to a silicide layer adjacent the second FET;
- performing an annealing operation to remove damage to the silicide layer and reduce silicide resistance after etching the first silicon nitride layer;
- and
- forming a second silicon nitride layer over the second FET.
Dependencies are inferred from the claim text.