Method of forming a MOS transistor
AssigneeUnited Microelectronics Corp.
InventorsHsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
Life of this patent
Estimating the term…
Abstract
A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, Chd xHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.
Claims18
A method of forming a MOS transistor, comprising:
- providing a substrate having a gate thereon, a source region and a drain region therein with a channel region under the gate therebetween;
- thereafter pre-amorphizing the source region and the drain region to form amorphized regions;
- thereafter performing a first ion implantation to implant a first dopant in the source region and the drain region to form a first doped region;
- thereafter forming at least a spacer on the sidewalls of the gate;
- thereafter performing a second ion implantation to implant a second dopant in the source region and the drain region to form a second doped region;
- thereafter annealing the source region and the drain region to activate the first dopant, regrow the amorphized regions to a substantially crystalline form, and form a junction profile;
- and
- performing a co-implantation process, after pre-amorphizing the source region and the drain region and before annealing the source region and the drain region, to implant an co-implant in the source region and the drain region, wherein the co-implant comprises CxHy+or (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000, and the first dopant comprises B, BF2,BwHz+, or (BwHy)m+, wherein w is a number of 2 to 30, z is a number of 2 to 40, and m is a number of 10 to 1000.
A method of forming a MOS transistor, comprising:
- providing a substrate having a gate thereon, a source region and a drain region therein with a channel region under the gate therebetween;
- pre-amorphizing the source region and the drain region to form amorphized regions;
- performing a first ion implantation to implant a first dopant in the source region and the drain region to form a first doped region;
- forming at least a spacer on the sidewalls of the gate;
- performing a second ion implantation to implant a second dopant in the source region and the drain region to form a second doped region;
- annealing the source region and the drain region to activate the first dopant, regrow the amorphized regions to a substantially crystalline form, and form a junction profile;
- and
- performing a co-implantation process, after pre-amorphizing the source region and the drain region and before annealing the source region and the drain region, to implant a co-implant in the source region and the drain region, wherein the co-implant comprises CxHY+or (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4to 20, and n is a number of 1 to 1000, and the first dopant comprises B, BF2, BwHz+, or (BwHz)m+, wherein w is a number of 2 to 30, z is a number of 2 to 40, and m is a number of 10 to 1000.
Dependencies are inferred from the claim text.