Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

A method of fabricating a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), said NFET and said PFET each having a channel region, said channel region of said PFET having a first strain and said channel region of said NFET not having said first strain, said method comprising:

• forming a PFET gate stack and an NFET gate stack over a main surface of a first semiconductor region having a first composition, each of said PFET gate stack and said NFET gate stack including a gate dielectric, a gate conductor overlying said gate dielectric and first spacers along walls of said gate conductor;
• recessing a portion of said first semiconductor region adjacent to said first spacers of said PFET gate stack while protecting another portion of said first semiconductor region adjacent to said first spacers of said NFET gate stack from being recessed;
• growing a second semiconductor region overlying said recessed portion of said first semiconductor region while preventing said second semiconductor region from growing on said another portion of said first semiconductor region adjacent to said first spacers of said NFET gate stack, wherein said second semiconductor region has a second composition lattice-mismatched to a first composition of said first semiconductor region, such that said second semiconductor region applies a first strain to said channel region of said PFET;
• recessing said second semiconductor region below said main surface of said first semiconductor region;
• and
• fabricating source regions and drain regions of said PFET adjacent to said PFET gate stack and fabricating source regions and drain regions of said NFET adjacent to said NFET gate stack.

A method of fabricating a field effect transistor (FET), said method comprising:

• forming a gate stack overlying a main surface of a first semiconductor region having a first composition, said gate stack including a gate dielectric and a gate conductor overlying said gate dielectric;
• recessing a portion of said first semiconductor region adjacent to said gate stack to a depth below said main surface;
• growing a second semiconductor region overlying said recessed portion of said first semiconductor region, wherein said second semiconductor region has a second composition lattice-mismatched to the first composition of said first semiconductor region, such that said second semiconductor region applies a first strain to said channel region of said FET;
• recessing said second semiconductor region below said main surface of said first semiconductor region;
• and
• fabricating source regions and drain regions of said FET adjacent to said gate stack.