Structure and method for forming asymmetrical overlap capacitance in field effect transistors
AssigneeInternational Business Machines Corporation
InventorHaining Yang
Life of this patent
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Abstract
A method for forming asymmetric spacer structures for a semiconductor device includes forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate. The gate structures are spaced such that the spacer layer is formed at a first thickness in a region between the gate structures and at a second thickness elsewhere, the second thickness being greater than said first thickness. The spacer layer is etched so as to form asymmetric spacer structures for the pair of adjacently spaced gate structures.
Claims17
A method for forming asymmetric spacer structures for a semiconductor device, the method comprising:
- forming a spacer layer over at least a pair of adjacently spaced gate structures disposed over a semiconductor substrate, wherein said gate structures are spaced such that said spacer layer is formed at first thickness in a region between said gate structures and at a second thickness elsewhere, said second thickness greater than said first thickness;
- and
- etching the spacer layer so as to form asymmetric spacer structures adjacent sidewalls of said pair of adjacently spaced gate structures.
A method for forming field effect transistor (FET) structures for a semiconductor device, the method comprising:
- forming at least a pair of adjacently spaced gate structures over a semiconductor substrate;
- forming a spacer layer over said adjacently spaced gate structures, wherein said gate structures are spaced such that said spacer layer is formed at first thickness in a region between said gate structures and at a second thickness elsewhere, said second thickness greater than said first thickness;
- etching the spacer layer so as to form asymmetric spacer structures adjacent sidewalls of said pair of adjacently spaced gate structures;
- and
- implanting said substrate with doped regions, said doped regions having asymmetric characteristics in accordance with said asymmetric spacer structures.
A method for forming field effect transistor (FET) structures for a semiconductor device, the method comprising:
- forming at least a pair of adjacently spaced gate structures over a semiconductor substrate;
- forming offset spacers adjacent sidewalls of said pair of adjacently spaced gate structures;
- forming extension regions in said substrate;
- forming a second spacer layer over said offset spacers said gate structures and said substrate;
- subjecting said second spacer layer to a single, angled ion implantation of a neutral species, said angled ion implantation originating from a single direction;
- etching said second spacer layer, wherein portions of said second spacer layer subjected to said angled ion implantation are etched at a faster rate than unexposed portions thereof, thereby forming asymmetrical second spacers adjacent said offset spacers;
- and
- implanting said substrate with source and drain regions.
Dependencies are inferred from the claim text.