Wire structure, a thin film transistor substrate of using the wire structure and a method of manufacturing the same

A thin film transistor array panel comprising:

• a gate wire formed on an insulating substrate and including a gate line, and a gate electrode connected to the gate line;
• a gate insulating layer covering the gate wire;
• a semiconductor pattern formed on the gate insulating layer;
• a data wire including source and drain electrodes formed on the semiconductor pattern, made of the same layer, and separated from each other, and a data line connected to the source electrode and intersecting the gate line to define a pixel area;
• a protective layer having a first contact hole exposing the drain electrode;
• a pixel electrode formed on the protective layer and connected to the drain electrode through the first contact hole,
• wherein at least one of the gate wire and the data wire comprises double layers of an adhesion layer and an Ag containing layer, the adhesion layer comprises one of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta and Ta alloy, and the Ag containing layer comprises Ag or Ag alloy,
• wherein the Ag containing layer is located on the adhesion layer, and
• the adhesion layer having thickness of equal to or less than 500 Å.

A thin film transistor array panel comprising:

• an insulating substrate;
• a gate wire formed on the insulating substrate and including a gate line, a gate electrode and a gate pad;
• a gate insulating layer formed on the gate wire and having a contact hole at least exposing the gate pad;
• a semiconductor pattern formed on the gate insulating layer;
• an ohmic contact pattern formed on the semiconductor pattern;
• a data wire formed on the ohmic contact pattern, having substantially the same planar shape as the ohmic contact pattern, and including a source electrode, a drain electrode, a data line, and a data pad;
• a protective layer formed on the data wire and a plurality of contact holes exposing the gate pad, the data pad, and the drain electrode;
• and
• a transparent electrode pattern electrically connected to the exposed gate pad, data pad and drain electrode,
• wherein at least one of the gate wire and the data wire comprises double layers of an adhesion layer and an Ag containing layer, the adhesion layer comprises one of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta and Ta alloy, and the Ag containing layer comprises Ag or Ag alloy,
• wherein the Ag containing layer is located on the adhesion layer, and
• the adhesion layer having thickness of equal to or less than 500 Å.

A method of manufacturing a thin film transistor array panel, the method comprising:

• forming a gate wire on an insulating substrate, the gate wire including a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line;
• forming a gate insulating layer;
• forming a semiconductor layer;
• depositing a conductive layer and patterning the conductive layer to form a data wire including a data line intersecting the gate line, a data pad connected to the data line, a source electrode connected to the data line and placed close to the gate electrode, and a drain electrode opposite the source electrode with respect to the gate electrode;
• forming a protective layer;
• patterning the protective layer together with the gate insulating layer to form a plurality of contact holes respectively exposing the gate pad, the data pad and the drain electrode;
• and
• depositing a transparent conductive layer and patterning the conductive layer to form a subsidiary gate pad, a subsidiary data pad and a pixel electrode respectively connected to the gate pad, the data pad, and the pixel electrode,
• wherein at least one of the formation of the gate wire and the formation of the data wire comprises:
• sequentially depositing double layers of an adhesion layer and an Ag containing layer;
• and
• patterning the double layers,
• wherein the adhesion layer having thickness of equal to or less than 500 Å.

A method of manufacturing a thin film transistor array panel, the method comprising:

• forming a gate wire on an insulating substrate, the gate wire having a gate line, and a gate electrode connected to the gate line;
• forming a gate insulating layer covering the gate wire;
• forming a semiconductor pattern on the gate insulating layer;
• forming a data wire on the gate insulating layer, the data wire comprising source and drain electrodes including substantially the same layer and separated from each other, and a data line connected to the source electrode;
• forming red, green and blue color filters and a first aperture exposing the drain electrode, the color filters including a photosensitive material containing red, green and blue pigments and covering the data wire;
• forming a protective layer covering the red, green and blue color filters;
• forming a first contact hole exposing the drain electrode;
• and
• forming a pixel electrode connected to the drain electrode through the first contact hole,
• wherein at least one of the formation of the gate wire and the formation of the data wire comprises:
• sequentially depositing double layers of an adhesion layer and an Ag containing layer;
• and
• patterning the double layers,
• wherein the adhesion layer having thickness of equal to or less than 500 Å.