Hybrid software/hardware transactional memory

A method of operating a computational system, the method comprising:

• executing a first transaction against a transactional memory space, the first transaction executing under control of a software transactional memory (STM) facility, wherein the STM facility ensures atomicity of STM transactions using one or more software synchronization constructs;
• executing, concurrently with the first transaction, a second transaction against the transactional memory space, the second transaction being presented to a hardware transactional memory (HTM) facility, wherein the HTM facility ensures atomicity of HTM transactions using hardware and without using software synchronization constructs;
• coordinating operation of the first transaction and the second transaction using a hybrid transactional memory coordination mechanism;
• wherein the first and the second transactions access at least one common transactable location.

An apparatus comprising:

• one or more processors;
• a shared memory accessible by the one or more processors and configured to allow concurrent access by threads executable on respective ones of the processors;
• a hardware transactional memory (HTM) interface to a transaction space defined in the shared memory, the HTM interface comprising hardware coupled between the one or more processors and the shared memory and configured to coordinate amongst concurrent HTM transactions without using software synchronization constructs;
• a transactable location ownership data structure instantiated in the shared memory to track ownership status of transactable locations in correspondence with execution of software transactional memory (STM) transactions targeting transactable locations in the transaction space;
• a hybrid transactional memory coordination mechanism configured to cause the hardware transactional memory (HTM) interface to treat those entries, if any, of the transactable location ownership encoding corresponding to targets of a HTM transaction as within the apparent scope of the HTM transaction to allow the HTM interface to detect conflict, if any, with concurrently executing ones of the STM transactions.

A method of making a computer program product for execution in a computer system that supports coordinated hybrid HW/SW transactional memory, the method comprising:

• preparing an executable functional sequence corresponding to a source representation of code that includes a transaction construct;
• and
• including in the executable functional sequence two alternative functional encodings corresponding to the transaction construct,
• wherein a first alternative functional encoding includes a software transactional memory (STM) encoding that includes operations to maintain, for targets of the transaction construct, entries of a transactable location ownership encoding in correspondence with execution of the transaction construct using an STM interface, and
• wherein a second alternative functional encoding causes a hardware transactional memory (HTM) interface to treat those entries, if any, of the transactable location ownership encoding corresponding to targets of the transaction construct as within the apparent scope of the transaction construct in correspondence with execution of the transaction construct using the HTM interface.

A computer-readable storage medium, comprising program instructions configured to implement:

• a hardware transactional memory (HTM) sequence executable in a multithreaded computational environment that supports both HTM accesses and software transactional memory (STM) accesses to a single transactional memory space,
• wherein the HTM sequence causes a corresponding HTM access to include in its apparent transactional scope at least a portion of a transactable location ownership encoding maintained in correspondence with concurrent STM accesses to the transactional memory space to allow a hybrid transactional coordination mechanism of a HTM interface to the transactional memory space to detect conflict, if any, with concurrently executing STM transactions;
• and
• wherein the HTM interface is configured to coordinate amongst concurrent HTM accesses without using software synchronization constructs.

A computer-readable storage medium, comprising program instructions configured to implement:

• corresponding software transactional memory (STM) and hardware transactional memory (HTM) sequences, wherein either or both of the STM and HTM sequences are executable in a particular multithreaded computational environment and wherein each corresponds to a same transactional access to be performed,
• wherein the HTM sequence causes a corresponding HTM transaction to include in its apparent transactional scope at least a portion of a transactable location ownership encoding maintained in correspondence with concurrent STM accesses, if any, to a transactional memory space to allow a hybrid transactional memory coordination mechanism of a HTM interface to the transactional memory space to detect conflict, if any, with concurrently executing STM transactions;
• and
• wherein the HTM interface is configured to coordinate amongst concurrent HTM accesses without using software synchronization constructs.

An apparatus comprising:

• at least one processor including an interface comprising hardware configured to coordinate amongst hardware-mediated transactions in a hardware transactional memory (HTM) without using software synchronization constructs;
• means for storing code executable on the processor to provide a software transactional memory (STM) interface, wherein the STM interface ensures atomicity of STM transactions using one or more software synchronization constructs;
• and
• means for coordinating operation of the hardware transactional memory and the software transactional memory interface for concurrent hardware-mediated and STM transactions targeting overlapping sets of transactable locations.