Method and apparatus for performing multiply-add operations on packed data

A computing system comprising:

• an addressable memory to store data;
• a processor including:
• a first storage area to store M packed data elements, the first storage area corresponding to a first N-bit source;
• a second storage area to store M packed data elements, the second storage area corresponding to a second N-bit source;
• a decoder to decode a first set of one or more instruction formats having a first field to specify the first N-bit source and a second field to specify the second N-bit source;
• an execution unit, responsive to the decoder decoding a first instruction of the first set of one or more instruction formats, to produce M products of multiplication of the packed data elements stored in the first storage area by corresponding packed data elements stored in the second storage area, and to sum the M products of multiplication pairwise to produce M/2 results representing M/2 sums of products;
• and a third storage area to store M/2 packed data elements, the third storage area corresponding to a N-bit destination specified by the first instruction to store the M/2 results;
• and a magnetic storage device to store said first instruction.